3rd CERN System-on-Chip Workshop

Session

Project Session #2

4 Oct 2023, 14:30

13/2-005 (CERN)

Conveners

Project Session #2

• Adrian Byszuk (CERN)

17. Gateware and Software Architecture for the DI/OT Project

Alen Arias Vazquez (CERN), Bernard Guncic, Vasileios Amoiridis (CERN)

04/10/2023, 14:30

Distributed I/O Tier is a versatile hardware platform for custom electronics in HL-LHC applications within the Accelerators and Technology Sector. This platform exists in two variants: high-performance (non-radiation-tolerant) and radiation-tolerant. The former incorporates the System Board (a.k.a. the crate controller), featuring the Zynq Ultrascale+ MPSoC. This MPSoC runs Linux and provides...

18. Bare-metal Programming on Zynq UltraScale+ for the FGC4 Power Converter Controller

Dariusz Jakub Zielinski (CERN), Martin Cejp (CERN)

04/10/2023, 15:00

The context:
The Electrical Power Converters group (SY-EPC) is currently in the process of developing the latest iteration of its power converter controller, known as FGC4. It is an embedded device, based on the DI/OT hardware platform, used to control, monitor, and diagnose power converters. The primary control algorithm runs on the system board featuring Xilinx’s Zynq UltraScale+ SoC. The...

19. Update on SoCs in ATLAS Detector Controls: The Embedded Monitoring Processor as Example

Dominic Ecker (Bergische Universitaet Wuppertal (DE))

04/10/2023, 15:50

SoCs are getting adopted extensively by ATLAS systems for the local control and monitoring of their back-end electronics due to their flexibility towards the hardware through the programmable logic but also the convenience provided for higher level software within the Linux platform running on the processing system. The interface to detector control back-end applications is achieved by...

21. A Versatile Data Acquisition System for Silicon Pixel Detectors Prototyping (CARIBOU)

Younes Otarid (CERN)

04/10/2023, 16:20

Caribou is a versatile data acquisition system used by multiple collaborative frameworks (CERN EP R&D, RD50, AIDAinnova) for the qualification of novel silicon pixel detector prototypes. The system is built around a common hardware, firmware and software base shared accross different projects, thereby drastically reducing the development effort and costs. The current version consists of a...

22. SoC Integration and Usage in the gFEX Hardware Trigger in ATLAS

Kristin Dona (University of Chicago (US))

04/10/2023, 16:50

The Global Feature Extractor (gFEX) is a hardware trigger module that has been recently installed and is in the commissioning process for Run 3 in the ATLAS experiment. The gFEX hardware design includes a Zynq Ultrascale+ SoC used for a variety of purposes. The custom Operating System (OS) used with the SoC is built using the Yocto Project integrated with Xilinx. This talk will discuss updates...

46. Update of the ATLAS Online SW DAQ-to-SoC Communication Prototype

Andrei Kazarov (University of Johannesburg (SA))

04/10/2023, 17:20

We are presenting an update of the prototype implementation of the DAQ to SoC communication library, provided by ATLAS DAQ Online Software group. The presented solution is lightweight, based on the HTTP protocol and Nginx software implementation of HTTP server and allows to organize command exchange between ATLAS Run Control framework and SoC controlled subsystems, typically during operations...