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Description
Wafer to wafer bonding offers an economic approach to interconnect all readout electronic chips with the solid-state sensor chips on the wafer by only one bonding step. This is a promising technology for the fabrication of 3D integrated hybrid modules for particle detection and timing layers in future particle detectors. The technology described in this paper combines the metal-metal interconnection of pixels by Cu-Sn pillar bumps and the wafer level bonding by a photo-patterned polymer layer. In comparison to the metal-oxide-hybrid bonding process established in the industry for high volume production the metal-polymer hybrid wafer to wafer bonding process is applicable for wafers with higher surface topography tolerances. A dedicated MEDIPIX3 chip size adapted test chip and wafer design was developed for the wafer to wafer bonding process development. The top and bottom wafers with co-designed die patterns allow face to face wafer alignment and bonding using a combination of a thermo-compression and soldering process regime. Special features are implemented in order to measure electrical resistance and pillar bump interconnection yield after finishing the complete process. Cu-SnAg pillar bumps and solderable Cu are deposited by electroplating on the top and bottom wafer, respectively, and will form the electrical interconnection between both sides of the wafer stack after bonding. A photosensitive polyimide is used as a bonding layer, either deposited on top wafer only or on both wafers. After the wafer bonding process additional wafer thinning and silicon etching steps complete the process chain in order to demonstrate the potential for ultra-thin hybrid chip stacks and to get access to the probe pads for the electrical measurement. The results of the first measurements and analytic results will be presented in this paper. In a second work package of the project the bonding process will be transferred to the fabrication of a functional hybrid wafer stack based on MEDIPIX/TIMEPIX3 wafer and planar sensor wafer and will include TSV formation and backside interconnection as well.
