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4th 28nm Mixed-Signal Design Workshop

→ Europe/Zurich
572/R-006 (CERN)

572/R-006

CERN
CERN ASICs Design Support, CERN EP-ESE
01_28nm_workshop_welcome.pdf
02_28nm_workshop_lab_instruction.pdf
28 nm Technology Introduction
Analog Back-End
Analog Front-End
Digital
Mixed-signal
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  • Monday 11 December
    • Overview of the 28nm technology
      • 1
        Welcome
        Speaker: Alessandro Caratelli (CERN, EPFL)
      • 2
        Technology Overview and designerโ€™s guidelines
        Speaker: Franco Nahuel Bandi (CERN)
      • 3
        Overview of the 28nm common design platform
        Speaker: Marco Andorno (CERN)
    • 10:40
      Coffee break
    • Overview of the 28nm technology
      • 4
        Total Ionizing Dose response of the 28nm technlogy
        Speaker: Giulio Borghello (CERN)
    • 12:00
      Lunch break
    • Analog design
      • 5
        Analog simulation with Explorer and Assembler
        Speaker: Helga Dornelas (Cadence)
      • 6
        Lab session (Analog simulation)
        Speaker: Helga Dornelas (Cadence)
    • 15:15
      Coffee break
    • Mixed-signal design
      • 7
        Mixed-signal simulation with Xcelium and Virtuoso
        Speaker: Helga Dornelas (Cadence)
      • 8
        Lab session (Mixed-signal simulation)
        Speaker: Helga Dornelas (Cadence)
  • Tuesday 12 December
    • Mixed-signal design
      • 9
        Lab session (Mixed-signal simulation)
        Speaker: Helga Dornelas (Cadence)
    • 10:30
      Coffee break
    • Analog design
      • 10
        Analog Backend VXL Best Practices
        Speaker: Philippe Carriere (CERN)
      • 11
        Lab session (Analog backend)
        Speaker: Philippe Carriere (CERN)
    • 12:00
      Lunch break
    • Analog design
      • 12
        Lab session (Analog backend)
        Speaker: Philippe Carriere (Cadence)
    • 14:45
      Coffee break
    • Mixed-signal design
      • 13
        Abstract generation
        Speaker: Philippe Carriere (CERN)
      • 14
        Lab session (Abstract)
        Speaker: Philippe Carriere (CERN)
    • Analog design
      • 15
        DRC/LVS with PVS
        Speaker: Philippe Carriere (Cadence)
      • 16
        Lab session (DRC/LVS with PVS)
        Speaker: Philippe Carriere (CERN)
  • Wednesday 13 December
    • Mixed-signal design
      • 17
        IP block integration (Liberty file and Abstract)
        Speaker: Marco Andorno (CERN)
      • 18
        Lab session (Liberty file)
        Speakers: Alessandro Caratelli (CERN, EPFL), Marco Andorno (CERN)
    • 10:00
      Coffee break
    • Digital design
      28nm-workshop_synthesis_implementation_flat.pdf
      • 19
        Digital flow introduction

        Main steps of the flow, tools, Flowkit

        Speaker: Erwan Dekhil (Cadence)
      • 20
        Single event effects hardening in digital design
        Speaker: Alessandro Caratelli (CERN, EPFL)
    • 12:00
      Lunch break
    • Digital design
      28nm-workshop_synthesis_implementation_flat.pdf
      • 21
        Timing constraints and synthesis
        Speaker: Erwan Dekhil (Cadence)
    • 14:45
      Coffee break
    • Digital design
      28nm-workshop_synthesis_implementation_flat.pdf
      • 22
        Lab session (TMR)
        Speakers: Alessandro Caratelli (CERN, EPFL), Marco Andorno (CERN)
      • 23
        Lab session (Synthesis and LEC)
        Speakers: Alessandro Caratelli (CERN, EPFL), Erwan Dekhil (Cadence), Marco Andorno (CERN)
  • Thursday 14 December
  • Friday 15 December
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