8th International "Hiroshima" Symposium on the Development and Application of Semiconductor Tracking Detectors, Taipei, Taiwan

Design and verification of an FPGA based bit error rate tester

8 Dec 2011, 09:00

7h

2nd floor reception hall, Activity Center (Academia Sinica)

POSTER Poster sessions Poster session

Speaker

Minglee Chu (Academia Sinica)

Description

In characterizing a serial data transmission link, Bit Error Rate (BER) test provides the most stringent measurement. We will present a BER tester implementation using the Altera Stratix GX/GT signal integrity development kits. The Stratix II GX tester operates up to 6.5 Gbps and the Stratix IV GT tester operates up to 10Gbps, both in 4 duplex channels, with information of each single bit flip stored for off-line analysis. The BER testers are used in irradiation and in-lab characterization of ASICs and other components. Results from those tests will be presented as demonstration to the functionality of these BER testers.

Presentation materials

Slides

Poster_Chu_hstd2011-vbert-ver4.pdf