Speaker
Prof.
Jingbo Ye
(Southern Methodist University (US))
Description
A 5 Gb/s 16:1 serializer ASIC has been developed using a commercial 0.25 um thin-film silicon-on-sapphire CMOS technology. This prototype has been evaluated against operational conditions in detector front-end environments of the proposed HL-LHC upgrade. A novel two channel array serializer ASIC is being designed to meet challenges in ultra-high data transmission in the range of 100 Gb/s for each front-end board. We will report the prototype measurement results and the array serializer ASIC design status.
Author
Prof.
Jingbo Ye
(Southern Methodist University (US))
Co-author
Prof.
Suen Hou
(IPAS)
