Verification with UVM for HEP Workshop

Europe/Zurich
572/R-006 (CERN)

572/R-006

CERN

Adithya Pulli (CERN), Alessandro Caratelli (CERN, EPFL), Marco Andorno (CERN), Matteo Lupi (CERN), Simone Scarfi' (CERN), Stefano Esposito (CERN)
Description

CERN ASIC Support and Foundry Services

CERN ASIC Support
Registration
Registration
13 / 13
Surveys
Verification with UVM for HEP survey
    • 09:00 09:20
      Welcome and introduction 20m
    • 09:20 10:30
      SystemVerilog accelerated verification using UVM
      Convener: Luca Brambilla (Cadence)
    • 10:30 10:45
      Coffee break 15m
    • 10:45 12:00
      SystemVerilog accelerated verification using UVM
      Convener: Luca Brambilla (Cadence)
    • 12:00 13:00
      Lunch break 1h
    • 13:00 15:15
      SystemVerilog accelerated verification using UVM
      Convener: Luca Brambilla (Cadence)
    • 15:15 15:30
      Coffee break 15m
    • 15:30 17:30
      SystemVerilog accelerated verification using UVM
      Convener: Luca Brambilla (Cadence)
    • 09:00 10:30
      SystemVerilog accelerated verification using UVM
      Convener: Luca Brambilla (Cadence)
    • 10:30 10:45
      Coffee break 15m
    • 10:45 12:00
      SystemVerilog accelerated verification using UVM
      Convener: Luca Brambilla (Cadence)
    • 12:00 13:00
      Lunch break 1h
    • 13:00 15:15
      SystemVerilog accelerated verification using UVM
      Convener: Luca Brambilla (Cadence)
    • 15:15 15:30
      Coffee break 15m
    • 15:30 17:30
      SystemVerilog accelerated verification using UVM
      Convener: Luca Brambilla (Cadence)
    • 09:00 10:30
      SystemVerilog accelerated verification using UVM
      Convener: Luca Brambilla (Cadence)
    • 10:30 10:45
      Coffee break 15m
    • 10:45 12:00
      SystemVerilog accelerated verification using UVM
      Convener: Luca Brambilla (Cadence)
    • 12:00 13:00
      Lunch break 1h
    • 13:00 15:15
      SystemVerilog accelerated verification using UVM
      Convener: Luca Brambilla (Cadence)
    • 15:15 15:30
      Coffee break 15m
    • 15:30 17:30
      SystemVerilog accelerated verification using UVM
      Convener: Luca Brambilla (Cadence)
    • 09:00 10:30
      Verification best practices for HEP
    • 10:30 10:45
      Coffee break 15m
    • 10:45 12:00
      Verification best practices for HEP
    • 12:00 13:00
      Lunch break 1h
    • 13:00 15:15
      Verification best practices for HEP
    • 15:15 15:30
      Coffee break 15m
    • 15:30 17:30
      Verification best practices for HEP