Verification with UVM for HEP Workshop

27 Feb 2024, 09:00 → 1 Mar 2024, 17:30 Europe/Zurich

572/R-006 (CERN)

Adithya Pulli (CERN), Alessandro Caratelli (CERN, EPFL), Marco Andorno (CERN), Matteo Lupi (CERN), Simone Scarfi' (CERN), Stefano Esposito (CERN)

CERN ASIC Support and Foundry Services

Welcome.pdf

Day 1 to 3 UVMA_1_2_6.print.lab.CERN.pdf (Protected) UVMA_1_2_6.print.lect.CERN.pdf (Protected)

Day 4

• DAY4_LAB.pdf
• DAY4_Session1.pdf
• DAY4_Session2.pdf

Tuesday 27 February

1 Welcome and introduction

SystemVerilog accelerated verification using UVM

Convener: Luca Brambilla (Cadence)

10:30 Coffee break

SystemVerilog accelerated verification using UVM

Convener: Luca Brambilla (Cadence)

12:00 Lunch break

SystemVerilog accelerated verification using UVM

Convener: Luca Brambilla (Cadence)

15:15 Coffee break

SystemVerilog accelerated verification using UVM

Convener: Luca Brambilla (Cadence)

Wednesday 28 February

SystemVerilog accelerated verification using UVM

Convener: Luca Brambilla (Cadence)

10:30 Coffee break

SystemVerilog accelerated verification using UVM

Convener: Luca Brambilla (Cadence)

12:00 Lunch break

SystemVerilog accelerated verification using UVM

Convener: Luca Brambilla (Cadence)

15:15 Coffee break

SystemVerilog accelerated verification using UVM

Convener: Luca Brambilla (Cadence)

Thursday 29 February

SystemVerilog accelerated verification using UVM

Convener: Luca Brambilla (Cadence)

10:30 Coffee break

SystemVerilog accelerated verification using UVM

Convener: Luca Brambilla (Cadence)

12:00 Lunch break

SystemVerilog accelerated verification using UVM

Convener: Luca Brambilla (Cadence)

15:15 Coffee break

SystemVerilog accelerated verification using UVM

Convener: Luca Brambilla (Cadence)

Friday 1 March

Verification best practices for HEP

10:30 Coffee break

Verification best practices for HEP

12:00 Lunch break

Verification best practices for HEP

15:15 Coffee break

Verification best practices for HEP