5th 28 nm Mixed-Signal Design Workshop

8 Apr 2024, 09:00 → 12 Apr 2024, 17:30 Europe/Zurich

593/R-013 (CERN)

CERN EP-ESE, CERN ICs Design and Technology Support

Monday 8 April

09:00 → 10:40 Overview of the 28nm technology

09:00 Welcome

Speaker: Alessandro Caratelli (CERN, EPFL)

09:20 Technology Overview and designer’s guidelines

Speaker: Franco Nahuel Bandi (CERN)

10:10 Overview of the 28nm common design platform

Speaker: Marco Andorno (CERN)

10:40 → 10:55 Coffee break

10:55 → 12:00 Overview of the 28nm technology

10:55 Total Ionizing Dose response of the 28nm technlogy

Speaker: Giulio Borghello (CERN)

12:00 → 13:30 Lunch break

13:30 → 15:15 Analog design

13:30 Analog simulation with Explorer and Assembler

Speaker: Helga Dornelas (Cadence)

13:50 Lab session (Analog simulation)

Speaker: Helga Dornelas (Cadence)

15:15 → 15:30 Coffee break

15:30 → 17:30 Mixed-signal design

15:30 Mixed-signal simulation with Xcelium and Virtuoso

Speaker: Helga Dornelas (Cadence)

16:00 Lab session (Mixed-signal simulation)

Speaker: Helga Dornelas (Cadence)

Tuesday 9 April

09:00 → 10:30 Mixed-signal design

09:00 Lab session (Mixed-signal simulation)

Speaker: Helga Dornelas (Cadence)

10:30 → 10:45 Coffee break

10:45 → 12:00 Analog design

10:45 Analog Backend VXL Best Practices

Speaker: Philippe Carriere (CERN)

11:00 Lab session (Analog backend)

Speaker: Philippe Carriere (CERN)

12:00 → 13:30 Lunch break

13:30 → 14:45 Analog design

13:30 Lab session (Analog backend)

Speaker: Philippe Carriere (Cadence)

14:45 → 15:00 Coffee break

15:00 → 15:50 Mixed-signal design

15:00 Abstract generation

Speaker: Philippe Carriere (CERN)

15:20 Lab session (Abstract)

Speaker: Philippe Carriere (CERN)

15:50 → 17:30 Analog design

15:50 DRC/LVS with PVS

Speaker: Philippe Carriere (Cadence)

16:10 Lab session (DRC/LVS with PVS)

Speaker: Philippe Carriere (CERN)

Wednesday 10 April

09:00 → 10:00 Mixed-signal design

09:00 IP block integration (Liberty file and Abstract)

Speaker: Marco Andorno (CERN)

09:15 Lab session (Liberty file)

Speakers: Alessandro Caratelli (CERN, EPFL), Marco Andorno (CERN)

10:00 → 10:15 Coffee break

10:15 → 12:30 Digital design

10:15 Digital flow introduction

Main steps of the flow, tools, Flowkit

Speaker: Erwan Dekhil (Cadence)

10:45 Single event effects hardening in digital design

Speaker: Alessandro Caratelli (CERN, EPFL)

11:30 Lab session (TMR)

Speakers: Alessandro Caratelli (CERN, EPFL), Marco Andorno (CERN)

12:30 → 13:30 Lunch break

13:30 → 15:15 Digital design

13:30 Timing constraints and synthesis

Speaker: Erwan Dekhil (Cadence)

15:15 → 15:30 Coffee break

15:30 → 17:30 Digital design

15:30 Lab session (Synthesis and LEC)

Speakers: Alessandro Caratelli (CERN, EPFL), Erwan Dekhil (Cadence), Marco Andorno (CERN)

Thursday 11 April

09:00 → 10:15 Digital design

09:00 Block-level implementation

Synthesis, floorplan

Speaker: Erwan Dekhil (Cadence)

10:15 → 10:30 Coffee break

10:30 → 12:00 Digital design

10:30 Block-level implementation

Placement, clock tree synthesis, routing

Speaker: Erwan Dekhil (Cadence)

12:00 → 13:30 Lunch break

13:30 → 14:45 Digital design

13:30 Lab session (Block-level implementation)

Speakers: Alessandro Caratelli (CERN, EPFL), Erwan Dekhil (Cadence), Marco Andorno (CERN)

14:45 → 15:00 Coffee break

15:00 → 17:30 Digital design

15:00 Lab session (Block-level implementation)

Speakers: Alessandro Caratelli (CERN, EPFL), Erwan Dekhil (Cadence), Marco Andorno (CERN)

Friday 12 April

09:00 → 10:15 Digital design

09:00 Hierarchical implementation

Top level analysis with use of block model, assemble design

Speaker: Erwan Dekhil (Cadence)

10:15 → 10:30 Coffee break

10:30 → 12:00 Digital design

10:30 Lab session (Hierarchical implementation)

Speakers: Alessandro Caratelli (CERN, EPFL), Erwan Dekhil (Cadence), Marco Andorno (CERN)

12:00 → 13:30 Lunch break

13:30 → 15:00 Digital design

13:30 Signoff

Timing analysis, power analysis, DRC, LVS

Speaker: Erwan Dekhil (Cadence)

15:00 → 15:15 Coffee break

15:15 → 17:30 Digital design

15:15 Lab session (Signoff)

Speakers: Alessandro Caratelli (CERN, EPFL), Erwan Dekhil (Cadence), Marco Andorno (CERN)