5th 28 nm Mixed-Signal Design Workshop

8 Apr 2024, 09:00 → 12 Apr 2024, 17:30 Europe/Zurich

593/R-013 (CERN)

CERN EP-ESE, CERN ICs Design and Technology Support

Monday 8 April

Overview of the 28nm technology

1 Welcome

Speaker: Alessandro Caratelli (CERN, EPFL)

2 Technology Overview and designer’s guidelines

Speaker: Franco Nahuel Bandi (CERN)

3 Overview of the 28nm common design platform

Speaker: Marco Andorno (CERN)

10:40 Coffee break

Overview of the 28nm technology

4 Total Ionizing Dose response of the 28nm technlogy

Speaker: Giulio Borghello (CERN)

12:00 Lunch break

Analog design

5 Analog simulation with Explorer and Assembler

Speaker: Helga Dornelas (Cadence)

6 Lab session (Analog simulation)

Speaker: Helga Dornelas (Cadence)

15:15 Coffee break

Mixed-signal design

7 Mixed-signal simulation with Xcelium and Virtuoso

Speaker: Helga Dornelas (Cadence)

8 Lab session (Mixed-signal simulation)

Speaker: Helga Dornelas (Cadence)

Tuesday 9 April

Mixed-signal design

9 Lab session (Mixed-signal simulation)

Speaker: Helga Dornelas (Cadence)

10:30 Coffee break

Analog design

10 Analog Backend VXL Best Practices

Speaker: Philippe Carriere (CERN)

11 Lab session (Analog backend)

Speaker: Philippe Carriere (CERN)

12:00 Lunch break

Analog design

12 Lab session (Analog backend)

Speaker: Philippe Carriere (Cadence)

14:45 Coffee break

Mixed-signal design

13 Abstract generation

Speaker: Philippe Carriere (CERN)

14 Lab session (Abstract)

Speaker: Philippe Carriere (CERN)

Analog design

15 DRC/LVS with PVS

Speaker: Philippe Carriere (Cadence)

16 Lab session (DRC/LVS with PVS)

Speaker: Philippe Carriere (CERN)

Wednesday 10 April

Mixed-signal design

17 IP block integration (Liberty file and Abstract)

Speaker: Marco Andorno (CERN)

18 Lab session (Liberty file)

Speakers: Alessandro Caratelli (CERN, EPFL), Marco Andorno (CERN)

10:00 Coffee break

Digital design

19 Digital flow introduction

Main steps of the flow, tools, Flowkit

Speaker: Erwan Dekhil (Cadence)

20 Single event effects hardening in digital design

Speaker: Alessandro Caratelli (CERN, EPFL)

21 Lab session (TMR)

Speakers: Alessandro Caratelli (CERN, EPFL), Marco Andorno (CERN)

12:30 Lunch break

Digital design

22 Timing constraints and synthesis

Speaker: Erwan Dekhil (Cadence)

15:15 Coffee break

Digital design

23 Lab session (Synthesis and LEC)

Speakers: Alessandro Caratelli (CERN, EPFL), Erwan Dekhil (Cadence), Marco Andorno (CERN)

Thursday 11 April

Digital design

24 Block-level implementation

Synthesis, floorplan

Speaker: Erwan Dekhil (Cadence)

10:15 Coffee break

Digital design

25 Block-level implementation

Placement, clock tree synthesis, routing

Speaker: Erwan Dekhil (Cadence)

12:00 Lunch break

Digital design

26 Lab session (Block-level implementation)

Speakers: Alessandro Caratelli (CERN, EPFL), Erwan Dekhil (Cadence), Marco Andorno (CERN)

14:45 Coffee break

Digital design

27 Lab session (Block-level implementation)

Speakers: Alessandro Caratelli (CERN, EPFL), Erwan Dekhil (Cadence), Marco Andorno (CERN)

Friday 12 April

Digital design

28 Hierarchical implementation

Top level analysis with use of block model, assemble design

Speaker: Erwan Dekhil (Cadence)

10:15 Coffee break

Digital design

29 Lab session (Hierarchical implementation)

Speakers: Alessandro Caratelli (CERN, EPFL), Erwan Dekhil (Cadence), Marco Andorno (CERN)

12:00 Lunch break

Digital design

30 Signoff

Timing analysis, power analysis, DRC, LVS

Speaker: Erwan Dekhil (Cadence)

15:00 Coffee break

Digital design

31 Lab session (Signoff)

Speakers: Alessandro Caratelli (CERN, EPFL), Erwan Dekhil (Cadence), Marco Andorno (CERN)