Focus on:  Hide Contributions
Login

SoC Interest Group Meeting: Demo/Presentation

→ Europe/Zurich
222/R-001 (CERN)

222/R-001

CERN

200
Show room on map
Christos Gentsos (CERN (IT-CA-GES)), Hamza Boukabache (CERN), Ralf Spiwoks (CERN)
FPGA-SoC workshop CERN.pdf
SoC Interest Group Meeting
Zoom Meeting ID
65172635208
Host
Ralf Spiwoks
Alternative host
Adrian Byszuk
Useful links
Join via phone
Zoom URL
    • 1
      MathWorks SoC Design Flows @ CERN

      This 3-hour workshop, presented by experts from MathWorks, offers a deep dive into the latest applications and best practices of Model-Based Systems Engineering (MBSE) and Model-Based Design (MBD) for System-on-Chip (SoC) design flows.

      Attendees will gain hands-on experience in floating point to fixed-point conversion, automatic code generation workflows for Field Programmable Gate Arrays (FPGAs) and SoCs, and optimizing code for performance. The workshop is specifically tailored for algorithm, system, and hardware engineers involved in configuring models for Hardware Description Language (HDL) code generation for deployment on FPGA, SoC, or Application-Specific Integrated Circuit (ASIC) platforms.

      Speaker: Stephan van Beek (MathWorks)
      • a) Introduction
      • b) Systems Engineering Workflows for FPGA/SoC

        • Managing Requirements
        • Function allocation to SoC platforms

      • c) Automatic HDL Code Generation and Verification

        • Converting Floating point to Fixed-point
        • Generating IP cores including AXI-interfaces
        • Verifying HDL code using HDL co-simulation (QuestaSim/Vivado)

      • d) Deploying Algorithms on SoC Platforms

        • Real-Time Code Execution Profiling
        • Generating Target-aware C-code for ARM
        • Full Algorithm Deployment on SoC

      • e) Summary and Next Steps
Powered by Indico v3.3.6-pre