SoC Interest Group Meeting

Friday Mar 8, 2024, 2:00 PM → 6:00 PM Europe/Zurich

40/S2-C01 - Salle Curie (CERN)

Ralf Spiwoks (CERN)

2:00 PM → 3:00 PM Tutorial on SoC Co-Simulation

A comprehensive co-simulation framework for System-on-Chip (SoC) serves as an invaluable tool for testing and verifying heterogeneous designs that incorporate complex HDL (Hardware Description Language) and operating systems under real-world conditions. This approach facilitates an in-depth exploration of the interactions between HDL, software, and real-world scenarios in ways that are unattainable through other means, while also streamlining the debugging process on actual hardware platforms.
In this presentation, we will showcase the implementation of co-simulation within the CROME system, employing a combination of a mixed-language RTL (Register Transfer Level) simulator, libsystemctlm, and QEMU. We will elucidate how these components integrate, highlight the compromises involved, and provide guidance on developing a similar co-simulation environment for your projects.

Speakers: Clyde Laforge (CERN), Hamza Boukabache (CERN)

Cosimulation.pdf

Recording

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3:00 PM → 3:30 PM Update on SoC Activities in the CERN AT Sector

Speaker: Irene Degl'Innocenti (CERN)

ATS SoC Taskforce_SoC_IG.pdf

ATS SoC Taskforce_SoC_IG.pptx

Recording

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