Speaker
Description
The Phase-2 Upgrade of the CMS Outer Tracker requires the manufacturing of 8000 Strip-Strip and 5880 Pixel-Strip modules, altogether incorporating 47520 hybrid circuits of 15 variants. To ensure complete functionality of the modules it is essential to perform production-scale testing of the hybrids before the module assembly. For that reason, a complex and scalable test system was designed, manufactured, and commissioned. However, difficulties with the system deployment exceeded expectations, which required extensive debugging and creative problem solving. The problems, solutions and lessons learned from the system deployment will be presented.
Summary (500 words)
The Compact Muon Solenoid (CMS) Outer Tracker Phase-2 Upgrade for the High Luminosity Large Hadron Collider (HL-LHC) is composed of two main types of modules: the strip-strip (2S) and the pixel-strip (PS). To construct these modules seven main types of hybrid circuits were designed, those are namely the 2S Front End Hybrids and 2S Service Hybrid for the 2S modules and accordingly PS Front End Hybrids, PS Readout Hybrid and PS Power Hybrid for the PS modules. Additionally, hybrids are produced in different variants depending on the module spacing, communication speed (5G or 10G readout) and hybrid side (right or left front end). Altogether 47520 hybrid circuits of fifteen variants are currently manufactured and will be finished in approximately 2 years.
The module assembly is taking place at collaborating institutes, where the different components are permanently glued together. In order to minimize losses during the module production it is imperative to assure that all components conform to the specification. To control the quality of the hybrids it is planned to visually inspect and functionally evaluate 100% of them. Given the needs of the project (high throughput, multiple hybrid types, operation temperature of 35°C) a versatile multiplexing test system has been developed, manufactured, and commissioned. The system consists of the multiplexing backplanes mounted in 3U 19-inch sub-rack, which can accommodate six different types of test cards with their corresponding mechanical components and accessories. The essential part of the system is the testing software, based on the Ph2 Acquisition and Control Framework, which communicates through IPBUS protocol with the FC7 FPGA board that controls the backplanes and processes the data. The development of testing hardware was finalized but scaling up the quantities and the throughput proved to be a challenging task, with various unexpected results, technical difficulties and lessons learned.
The contribution will first give an overview of test system components and the commissioning exercise conducted on them. Then it will discuss difficulties related to qualification of the test system hardware in large scale i.e., calibration, fusing and mechanical assembly of nearly 500 test cards with limited numbers of reference hybrids in addition to the qualification of thousands of jumpers and adaptors. The presenter will put emphasis on the debugging of the full system, including hardware, firmware, and software related failures, namely: difficulties with timing and quality of signals, thermal drift of certain parameters and discontinued software support. The presentation will elaborate on the encountered difficulties, experiences gained from the deployment of the system at the manufactured premises, and qualitative criteria concerning the reliability, high-throughput, and safety of the system, with emphasis on the development and functionality of test system monitoring tool. As the summary the author will provide advice for future test system engineers based on the learning experiences faced in the project. Current measurement data will be shown concerning the real throughput, test times, and repeatability of test results.
