30 September 2024 to 4 October 2024
Europe/London timezone

Electrical measurement and read-out performance of a realistic, full-scale system bench of CMS Inner Tracker Barrel for HL-LHC

3 Oct 2024, 11:40
20m
Oral System Design, Description and Operation System Design, Description and Operation

Speaker

Giulio Bardelli (Universita e INFN, Firenze (IT))

Description

The harsh environment of the High-Luminosity Phase of LHC will force the CMS experiment to replace the present pixel detector with a new Inner Tracker implementing 65 nm CMOS read-out chips (CROC). The modules, i.e. the Inner Tracker subunits, are powered in series and read-out through a sophisticated opto-electrical chain. Full-scale systems are realized and tested for validation and performance assessment. The latest results obtained with a serial chain of the final prototypes CROC modules for the TBPX sub-detector will be presented. This system test also implements prototype mechanics and the final electrical opto-conversion stage.

Summary (500 words)

The high pile-up and the radiation damage experienced at HL-LHC represent a challenge for the new CMS innermost pixel tracking system (Inner Tracker, IT), deployed in the context of the Phase-2 upgrade to cope with the HL-LHC experimental conditions.

The smallest basic unit that equips this new detector is the module formed by 2 (double) or 4 (quad) CROCs (CMS Read-out Chip, designed in 65nm CMOS technology), planar or 3D sensors and a High Density Interconnect (HDI). Modules are powered in series with ~2A per CROC, thanks to the current-driven Shunt-LDO regulator and mounted on a carbon fiber structure that embeds the cooling pipes of the CO2 cooling system. The read-out chain consists, upstream, of electric links (e-links) between the modules and an opto-conversion board (portcard) connected to the back-end electronics (DTCs) via optical fibers. The e-links for TPBX (barrel) IT subdetector are bundles of 5x twisted pairs (4x data lanes and 1x command lane). The portcard hosts 3x LpGBT (Low Power Giga Bit Transceiver) each driving a VTRx+ laser modulator.

A serial chain of 8 full-scale prototypes digital (i.e. with no sensor) quad modules equipped with CROC-v1 is mounted in the prototype of the mechanical structure and CO2 cooled at temperatures of the coolant liquid ranging between 10 °C and -35 °C. Initially, the readout is fully electrical. "Figure_1.png" shows the set-up. The first results obtained with a serial chain of 8 quad modules powered with 8A and CO2 cooled down to -35 °C are presented.

The stability of the system is also studied as a function of the input current, assessing the stability of the system down to 10% headroom (i.e. the current in excess needed by the Shunt-LDO to function properly), meeting the expected requirement of operability with headroom higher than 20%.

As an evolution of the system verification and validation, the final read-out chain has been implemented with the e-links, portcard and optical fiber prototypes, making this second set-up a more realistic replica of the TBPX towards the upgraded detector. The read-out performance has been compared with the full electrical read-out. The results are presented in terms of noise and threshold dispersion. In both cases the noise is below 90 e- and the threshold dispersion is uniform around 50 e- (for a threshold of about 1100e-). "Figure_2.png" and "Figure_3.png" show, respectively, the noise for the electrical read-out and for the optical one.

The bit error rate (BER) tests, consisting of sending 10^{10} frames (32 bit) at 1.28 Gbps, demonstrate the read-out stability and reliability also thanks to the pre-emphasis feature implemented in the system. The two read-out methods show comparable results down to Frame error rate of 10^{-10}. The communication has also been studied as a function of the overshoot of the pulse (10 bit) and as a function of the BER proving efficient communication during tuning even with Frame Error Test at 10^{-8}. This test is shown in "Figure_4.png".

Latest additions foreseen are the power cables and the power supply prototypes developed for Phase II.

Primary author

Giulio Bardelli (Universita e INFN, Firenze (IT))

Presentation materials