Conveners
ASIC
- David Gascon (ICCUB)
- Marcus Julian French (Science and Technology Facilities Council STFC (GB))
ASIC
- Marcus Julian French (Science and Technology Facilities Council STFC (GB))
- David Gascon (ICCUB)
ASIC
- David Gascon (ICCUB)
- Ping Gui (Southern Methodist University (US))
ASIC
- Ping Gui (Southern Methodist University (US))
- David Gascon (ICCUB)
ASIC
- Angelo Rivetti (INFN - National Institute for Nuclear Physics)
- Christine Guo Hu (Centre National de la Recherche Scientifique (FR))
ASIC
- Ping Gui (Southern Methodist University (US))
- Marcus Julian French (Science and Technology Facilities Council STFC (GB))
ASIC
- Angelo Rivetti (INFN - National Institute for Nuclear Physics)
- Christine Guo Hu (Centre National de la Recherche Scientifique (FR))
ASIC
- Angelo Rivetti (INFN - National Institute for Nuclear Physics)
- Christine Guo Hu (Centre National de la Recherche Scientifique (FR))
With over 6 million channels, the High Granularity Calorimeter (HGCAL) for the CMS HL-LHC Upgrade presents a unique data challenge. The ECON ASICs provide critical on-detector data reduction for the 40 MHz trigger path (ECON-T) and 750 kHz data acquisition path (ECON-D) of the HGCAL. The ASICs, fabricated in 65nm CMOS, are rad-tolerant (600 Mrad) with low power consumption (<2.5 mW/channel)....
The High-Granularity Calorimeter (HGCAL) of CMS will undergo a major upgrade during the Long-Shutdown 3. The Endcap Concentrators (ECON) ASICs represent key elements in the readout chain, processing trigger (ECON-T) and data (ECON-D) streams from the HGCROC to the LpGBT. The ECONs will operate in a radiation environment with a High-Energy Hadron (HEH) flux of $3\cdot10^{6}...
Many high-energy physics experiments require high-data-rate links between readout ASICs and digital back-end processors over lossy channels, such as radio-pure cables. The preferred solution uses a forwarded clock architecture in which the back-end transfers a low-frequency reference clock (e.g., from a crystal oscillator) to the readout system over a low-speed cable, which is then used by a...
As front-end ASIC complexity in HEP experiments grows, there is a shift towards more modular, programmable, and cost-effective designs. This work introduces the SOCRATES platform, a radiation-tolerant SoC generator toolset, centered on SoCMake, a hardware/software build system that automates SoC assembly and verification. Utilizing existing IP blocks, SoCMake generates the interconnects and...
High pileup densities imply new challenges. In this context, 4D tracking with a timing resolution of ~10ps is essential for track reconstruction. For Muon Colliders, precise timing information becomes indispensable to mitigate the Background Integrated Beam (BIB). Therefore, a high-precision Time-To-Digital (TDC) stands as a crucial component in realizing 4D tracking. In 2023, we introduced...
The FAST3 (Fast Amplifier for Silicon detector for Timing) is a low noise 16-channel ASIC, belonging to the FAST ASIC family. FAST3 has been implemented in UMC 110 nm CMOS technology, and the design has been optimized for the read-out of 50µm-thick LGAD (Low-Gain Avalanche Diode). The figure of merit of FAST3 is the excellent temporal jitter below 20ps in a wide dynamic range of input charge...
The Endcap Timing ReadOut Chip (ETROC) is designed to process LGAD signals with time resolution down to ~ 40-50ps per hit. The ETROC2 is the first full size prototype design fully compatible with the final chip specifications for CMS ETL. The ETROC2 chips have been extensively tested over the past year since May 2023, with laser, hadron beam at CERN and electron beam at DESY, with temperature...
The IGNITE project develops technical solutions for the next generation of trackers at colliders. It plans to implement an integrated module, comprising sensor, electronics, and fast readout, aimed at fast 4D-tracking. System pixels are required to have pitch around 50 µm and time resolution below 30 ps. In the present paper we present measurement results concerning the performance of the...
Highly granular precision timing detectors are required to achieve scientific breakthroughs across HEP, NP, BES, and FES. To enable the development of these detectors, 3D-intgration between advanced sensor wafers and scaled CMOS technology nodes is required but is currently cost-prohibitive for use in scientific applications. Closing this technology gap is the joint SLAC, FNAL and LLNL effort...
Following the ALICE ITS3 detector development line of wafer-scale monolithic stitched pixel detector prototypes in the TPSCo. 65nm CMOS imaging technology, the MOSAIX chip is the prototype of the final full-size and full-functionality ITS3 sensor.
MOSAIX has a die size of 26.6x1.96 cm2 with >94% of active area. It has 144 sensor tiles which can be powered individually to compensate for...
For the LS3 ALICE ITS3 upgrade the detector material budget reduction has been pushed to the limit by proposing a system composed almost exclusively of silicon wafer thinned to 50$\,\mu\mathrm{m}$. This improves performance, but adds complexity to the ASIC design. It requires a wafer-scale module with embedded power delivery network and on-chip data transfer, which were usually done through...
The Monolithic Stitched Sensor (MOSS) is a prototype silicon pixel sensor of $26~\textrm{x}~1.4~\textrm{cm}^2$ size with the primary goal of understanding the stitching technique and yield. It is a proof-of-concept chip for the final sensors of the ALICE ITS3 upgrade. Given the large size, high yield is paramount for the ITS3 sensors and an in-depth yield characterization was performed on MOSS...
The MOSS wafer-scale monolithic sensor, designed for the vertex detector (ITS3) of the ALICE experiment, features a pixel input capacitance of ~5fF. Such a small input capacitance is needed to reach a satisfactory SNR with a low-power analog front-end (30nW/pixel). This makes the design of the pulsing circuitry needed to characterize the front-end performance particularly challenging. As an...
The ASIC for the high-granularity pre-shower detector of the FASER experiment at CERN is a full-reticle imaging chip (1.5x2.2 cm^2) for TeV-scale electromagnetic showers at the LHC. It features a monolithic pixel sensor with 65 µm side hexagonal pixels in IHP 130nm SiGe BiCMOS. The pixels integrate analog memories for charge measurement (0.5 fC÷64 fC) and the frontend with 100-ps-level jitter...
The RD50-MPW prototypes are High Voltage CMOS pixel chips in the 150 nm technology from LFoundry S.r.l. aimed at developing monolithic silicon sensors with excellent radiation tolerance, fast timing resolution and high granularity for tracking applications in future challenging experiments in physics. RD50-MPW4, the latest prototype within this programme, implements significant improvements...
The HKROC is designed to read out the Photo Multiplier Tubes (PMTs) for next-generation neutrino experiments, which involve multi-ton detector with thousands of PMTs. It measures and digitizes the charge (up to 2500 pC) and Time-of-Arrival (ToA) (25 ps), transmitting this data to the back-end electronics. A second prototype of the HKROC, submitted in CMOS 130 nm node by summer 2022, aimed to...
ALTIROC3 is a 2x2 cm² CMOS 130nm ASIC with 225 channels to read-out the new ATLAS HGTD detector for the High Luminosity-LHC upgrade. It was designed using “Digital-On-Top” flow and triplicated for radiation hardness. Chip level IR-Drop analyses were performed to evaluate accurately the power distribution impact, especially for the Time- to- Digital- Converters implemented in each pixel. These...
The Cleopatra ASIC is a 12-channel prototype ASIC for the readout of hydrogenated amorphous silicon sensors used for real-time dosimetry in radiation diagnostic and radiation therapy.
The architecture is based on a current to frequency conversion based on the recycling integrator principle in order to cover a dynamic range of four orders of magnitude with high linearity.
Three different...
A High-Voltage CMOS (HV-CMOS) pixel sensor for particle detection in high energy physics experiments, named UKRI-MPW1, has been developed. It has a high breakdown voltage of ~700 V, while keeping the leakage current below 100 $\mathrm{nA/cm^2}$. This is achieved by improving the sensor cross-section with a customised P-Shield layer and using an advanced chip guard ring scheme. With high...
This work presents the design of a 4-channel ASIC developed in a 65 nm CMOS technology specifically designed to measure the energy captured by the PMTs in the LHCb Upgrade II Calorimeter. The processing chain stands on rail-to-rail fully differential blocks that improve the common noise rejection and maximize the voltage range. A dual gain structure is adopted to extend the dynamic range up to...
Multi-channel analog-to-digital converters (ADCs) operating over a wide temperature range are required for data acquisition in high-energy physics experiments, space missions, medical imaging, astronomy, and quantum computing. For example, charge readout of the liquid argon (LAr) time projection chambers (TPCs) used by the DUNE far detectors relies on cooled ADCs operating at 89K. Successive...
