The Belle II experiment searches for physics beyond the standard model. Among the intriguing candidates are decays with an offset vertex. However, the current level-1 trigger dismisses these candidates. To address this problem, a new trigger system is required that can identify such decays when they exhibit two tracks from an offset vertex. The approach uses parallel calculations of Hough...
Accurate time measurement is essential for future high-energy physics experiments, such as Calorimeters and Time of Flight detectors of the Circular Electron Positron Collider (CEPC). The advancement of detector performance necessitates the need of high-resolution timing circuits. We introduce a ring-oscillator based timing block controlled by a delay locked loop, employing passive...
The GRAiNITA prototype has been developed as a first step toward the development of a next-generation calorimeter for FCC-ee. To evaluate GRAiNITA performance, a special test bench was built. The principle consists in tracking the cosmic ray muons that pass through the prototype to check the response of it as a function of the region traversed. Wavelength-shifting fibers capture the light...
This work describes the design, in a 28 nm CMOS technology, of a front-end channel for the readout of pixel sensors in future particle accelerators. The channel being developed leverages the Time-Over-Threshold technique for the numerical conversion of the detector signal amplitude, and includes a low-noise charge sensitive amplifier featuring a compact gain stage architecture. A prototype...
Quality analogue radiation-hardened design in 28nm CMOS is an iterative process best achieved through IP development. Rutherford Appleton Laboratory (RAL) ASIC Design Group has implemented two test-structure ASICs, PURNIX and YELNIX, to validate the performance of circuits up to 1GRAD TID. PURNIX includes essential building-block radiation-hardened IP, while YELNIX includes a prototype LGAD...
The CMS Collaboration will replace its current endcap calorimeters with a new high granularity calorimeter (HGCAL) for operations at the HL-LHC. The HGCAL back-end DAQ system comprises 96 FPGA-based ATCA boards, each processing data from 108 input optical fibres operating at 10 Gb/s. This paper describes in detail the architecture and prototyping of the elementary readout unit in the back-end...
At PSI the future standard hardware platform based on CompactPCI-Serial is already widely spread for developments in several applications and is under discussion for use on all our accelerators.
With the focus on cost optimization smaller sub-racks are now part of the toolbox as well as rear boards with a subtle set of interfaces.
Based on the requirements of a Fill-Pattern Monitor for SLS...
CosmoLink is a compact coincidence detector comprising two scintillators for portable on-site muon flux measurement. The Scintillators are coupled with wavelength shifting (WLS) fibers for efficient light guiding to Silicon photomultipliers (SiPMs). Each readout channels equipped with a Transimpedance preamp, Discriminator and peak hold circuit. Upon successful coincidence trigger the peak...
Before starting the High-Luminosity Large Hadron Collider (HL-LHC) runs, the CMS detector will be substantially upgraded to cope with the significant increase in instantaneous luminosity. The entire CMS Inner Tracker (IT) detector will be replaced, and the new detector will feature increased radiation hardness, higher granularity, and the capability to handle higher data rates and longer...
The Taishan Antineutrino Observatory (TAO) aims to measure the energy spectrum of reactor antineutrinos, providing a reference spectrum for the JUNO and offering benchmark references for the nuclear databases.
The JUNO-TAO experiment uses 4024 SiPM tiles with 8048 ADC channels to ensure the proposed energy resolution(<1.5% @ 1 MeV), spatial resolution(around 1 cm), and timing...
We developed signal readout electronics for a liquid argon time projection chamber detector, envisioned for use in neutrino oscillation and nucleon decay search experiments. The front-end electronics are based on the ASIC technology, which consists of a 16 channels analog processor, an analog-to-digital converter, and a signal transmitter for digital processing. We demonstrated that the...
The High-Luminosity LHC will start operations for physics in 2029.
The expansion of the dataset will be achieved by increasing the number of collisions per bunch crossing, leading to higher radiation doses and busier events. To cope with those harsher conditions, the ATLAS Liquid Argon Calorimeter readout will be upgraded to be able to efficiently measure the deposited energies.
A new...
The design and measurement results of a prototype TDC fabricated in CMOS 130nm technology are presented. The TDC architecture with analog interpolators was chosen, which was motivated by previous experience in ADC design. The measured time difference between the event and the trigger signal is converted to the amplitude and then digitised by a 10-bit ADC. The TDC prototype is functional nad...
The ASIC EICROC is designed to read out the AC-LGAD detectors for the future EIC at Brookhaven National Laboratory (BNL). These detectors should combine excellent temporal (20 ps) and spatial (20 um) resolution, enabling a new generation of pixel detectors with precise time measurement. Designing an ASIC to read out the AC-LGAD detector represents a significant technological challenge. EICROC...
The Embedded Monitoring Processor (EMP) is a state-of-the-art multi-processing System on Chip (MPSoC) based platform, designed for the Detector Control System (DCS) of the ATLAS experiment upgrade. Utilizing the advanced capabilities of the Xilinx Ultrascale+ architecture, the EMP interfaces with the monitoring and control functionalities of its radiation hard front-ends through high-speed...
In preparation for the operation at HL-LHC the electronics of the Electromagnetic calorimeter Barrel must be replaced. 12240 new very front end (VFE) cards will amplify and digitize signals of 62100 lead-tungstate crystals instrumented with avalanche photodiodes. 2448 low voltage regulator cards provide power for the VFE and digital interface cards. Reliable operation of these cards with...
During the upcoming Long Shutdown (LS3) of the LHC, the three innermost layers of the ALICE Inner Tracking System (ITS2) will be replaced by ITS3, a new vertex detector utilizing curved, stitched wafer-scale monolithic silicon sensors, fabricated using 65 nm CMOS technology and thinned to 50 μm. The feasibility of this technology for ITS3 was examined in the initial test production run (MLR1)....
The STS detector in the CBM experiment delivers data via multiple E-Links connected to GBTX ASICs. In the process of data aggregation, that data must be received, combined into a smaller number of streams, and packed into so-called microslices containing data from specific periods. The aggregation must consider data randomization due to amplitude-dependent processing time in the FEE ASICs and...
The ATLAS Strip Tracker for HL-LHC consists of individual modules of silicon sensors and front-end electronics. The modules are mounted on carbon-fiber substructures with 14 modules per side. An End-of-Substructure (EoS) card connects up to 28 data lines to lpGBT and VL+ ASICs that provide data serialization and 10 GBit/s optical data transmission to off-detector systems, respectively. The EoS...
New-generation physics detectors create a need for high-speed, high-flexibility datalinks in the community. Specific interest lies with commercial standards, compatible with off-the-shelf hardware, therefore replacing custom backends.
We present encouraging first results of an effort evaluating 100Gb/s Ethernet for data readout in the context of typical High-Energy Physics detector...
MightyPix is the first iteration of a High-Voltage CMOS (HV-CMOS) sensor chip developed for the LHCb Mighty Tracker. The digital readout of this chip is compatible to LHCb specifications. To verify the digital functionality of the chip in an LHCb environment, an emulator has been developed . This setup comprises the FPGA, CERN's developed VLDB, some custom interface boards and support...
Next generation particle physics experiments like Electron Ion Collider (EIC) demand high-speed data communication and lower mass designs for its detectors.
This poster presents initial test results for circuits designed to meet the EIC high-speed data requirements. These include a dual-frequency Phase Locked Loop (PLL) that supports two frequency modes of operation, a 5 GHz Pseudo-Random...
Abstract: We present the architectural design, prototype fabrication and first measurements for the second revision of the High Pitch digitizer System-on-Chip (HPSoC) prototype. The HPSoC concept is that of a high channel density and scalable waveform digitization ASIC with an embedded interface to advanced high-speed sensor arrays such as e.g. AC-LGADs. The chip was fabricated in 65nm...
ITk strip module is the basic unit in ITk strip upgrade. To do an irradiation test for module with smaller size, the collaboration developed a board called BETSEE. We finish BETSEE test with all latest version of ASICs using proton beam at China Spallation Neutron Source, which is the first time using 10(Mrad/h) level dose rate. From our result, SEE effect is acceptable but TID effect become...
The ATLAS collaboration will replace its inner detector by an all-silicon tracker for the HL-LHC.
The new pixel detector will cover a sensitive area of 13m2 with about 9000 modules, made of planar and 3D silicon sensors bump bonded to new Front-End ASIC.
The modules are loaded on carbon structures in the form of (half)rings and staves.
Electrically functional prototypes of these local...
A new on-detector power distribution scheme for the High Granularity Calorimeter (HGCAL) Phase-2 upgrade of CMS is under development. This scheme is based on a heavy-copper flexible printed circuit board (FPC), allowing for an efficient use of the tight integration space, with minimal insulation overhead, excellent electrical and thermal performance and simplified integration, when compared...
The performance of ASICs for high-bandwidth communications is heavily influenced by the interconnection with the hosting module and paired devices, including the bonding scheme and the PCB layout. The validation campaign of the DART28 high-speed transmitter has highlighted that a coordinated simulation and design of the power delivery network is required to obtain satisfactory performance. In...
Silicon particle detectors struggle to follow the miniaturisation of available commercial processes, partially due to the relatively large transistors required for the optimal performance of the analogue frontend. Particam instead uses a digital only approach which is focused on digital storage cells switching due to transient radiation. With a pixel being little more than a memory cell it can...
High-precision time measurements are the latest trend for experiments and PET applications.
Compactness, scalability and applicability to thousands of channels is required for the readout electronics.
CAEN A5203 board, part of a synchronizable and distributable Front-End Readout System (FERS), integrates the CERN picoTDC ASIC on a small unit for high-resolution time measurements of ToA and...
Developing a cost-effective single-die pixel-detector hybridization method using Anisotropic Conductive Films (ACF) or Anisotropic Conductive Paste (ACP) aims to replace fine-pitch bump bonding with conductive micro-particle embedding in adhesive film or paste. This technology enables integration of hybrid or monolithic detectors in modules, replacing wire bonding or solder-bumping. Within the...
NνDEx-100 is the phase I of NνDEx, which is a proposed 0νββ detection experiment based on the high pressure gaseous TPC filled with SeF6. Thousands of sensors will be placed on the readout plane located in one end-cap of the TPC. The sensors collect ions, measure the charge and output analog waveforms with the integrated CSA. The outputs are then digitized, aggregated, and transmitted to the...
Next-generation silicon pixel detectors with fine granularity will allow for precise measurements of particle tracks in both space and time. A reduction in the size of pixel data must be applied at the collision rate of 40MHz to fully exploit the pixel detector information of every interaction for physics analysis.
We developed radiation hard readout integrated circuit with on-chip digital...
Results are presented for reliability tests of the SFP+ transceivers and the readout board of Thin Gap Chambers (TGC) for the ATLAS experiment at HL-LHC. The radiation tolerance was evaluated for the SFP+ transceivers from Broadcom and FS and the TGC frontend board with gamma ray irradiation up to O(100) Gy at the Cobalt-60 facility of Nagoya University. An accelerated aging test was also...
The ALICE experiment at the Large Hadron Collider (LHC) has planned an upgrade of the Inner Tracking System, ITS3, which will be installed during the LHC Long Shutdown 3 (LS3, 2026-2028). This presentation will show fresh results about the resolution performance obtained at the end of 2024 with 65 nm CMOS MAPS Analogue Pixel Test Structures during beam tests at CERN SPS. Resolution performance...
To cope with the increase of the LHC instantaneous luminosity, new trigger readout electronics were installed on the ATLAS Liquid Argon Calorimeters.
On the detector, new electronic boards digitise 10 times more signals than the legacy system. Downstream, large FPGAs are processing up to 20 Tbps of data to compute the deposited energies. Moreover, a new control and monitoring infrastructure...
The Global Trigger will be the final stage of the new Level-1 trigger for Phase-2 operation of CMS. Based on high-precision inputs from the muon-, calorimeter-, track- and particle flow triggers, it will evaluate a menu of O(1000) cut-based and machine-learning-based algorithms in a system of up to thirteen Serenity processing boards equipped with AMD Ultrascale+ FPGAs and interconnected with...
High-voltage CMOS Pixel technology is being considered for future Higgs factory experiments. The ATLASPix3.1 chip, with a pitch of 50μm x 150μm, fabricated using TSI 180nm HV-CMOS technology, is a full reticle-size monolithic HV-CMOS sensor with shunt-low dropout regulators that allow serial powering for multiple sensors. A beam test was conducted at DESY using 3-6 GeV positron beams, with...
The ATLAS experiment is preparing for the High-Luminosity LHC era, by replacing the current innermost detector with an advanced all-silicon tracker (pixels and strips) to withstand radiation damage and increased particle activity. Pixel module quality control spans various production stages which necessitates a robust data acquisition software capable of handling high data rates and MHz...
In this talk, we report the R\&D program underway at CCNU to develop a pixel chip for the readout of GEM detectors appropriate for use in the CSR external-target experiment (CEE) at HIRFL for beam monitoring. The chip offers simultaneous time-over-threshold (TOT) and time-of-arrival (TOA) measurements, and a data-driven readout scheme with a rate of 40 MPixels/s. Two generations of the chips...
