Ever more precise time information is required to separate independent events at planned and proposed particle physics experiments. Typically, a combination of internal gain, very fast amplifiers and complex sampling circuitry are used to achieve this high time resolution. In this contribution a novel circuit to improve the time resolution of a depleted monolithic active pixel sensor (DMAPS)...
We present the R&D of FPMROC, an ASIC for ToF-PET with a fast MCP-PMT (FPMT). The design architecture includes a preamplifier, a discriminator with programmable threshold, a time- to-digital converter, an event builder with a serializer, a clock unit, and a SPI. We aim for a time resolution below 10 ps, matching the targeted FPMT parameters. We are designing the first prototype using a 55 nm...
The upcoming ATLAS Phase II upgrade mandates replacing the tracking system with the all-silicon Inner Tracker (ITK), featuring a pixel detector as its core element. The monitoring data of the new system will be aggregated from an on-detector ASIC, Monitoring Of Pixel System (MOPS), and channeled to the Detector Control System (DCS) via a newly developed FPGA-based interface known as MOPS-Hub....
In High Energy Physics, ASICs are becoming more and more complex with the integration of many digital processing and monitoring structures. The next generation of System-On-Chips will require reprogrammable logic to let the user change the ASIC behavior after its fabrication. CPROC (Central Processing ReadOut Chip) is a processor demonstrator based on the RISC-V Instruction Set Architecture....
JUNGFRAU is a state-of-the-art charge-integrating detector for imaging experiments at synchrotrons and free-electron lasers. It is currently limited to a frame rate of 2.2 kHz. With the goal to increase the frame rate of the detector to > 10 kHz, we have designed a 3.125 Gbps high-speed serial readout recently. Thus, the development of a fast Analog-To-Digital Converter ADC has become our...
The CMS Electromagnetic Calorimeter (ECAL) uses lead tungstate scintillating crystals to measure the energy of electrons and photons produced at the Large Hadron Collider (LHC). The High Luminosity upgrade of the LHC (HL-LHC) at CERN during the LHC Long Shutdown 3 imposes significant challenges for its experiments. The higher luminosity changes the environmental conditions in which the ECAL...
The design and simulation results of an ultra-low power fast 10-bit SAR ADC in CMOS 130~nm technology, are presented. This ADC is an extension of experimentally verified (INL,DNL $<$ 0.5~LSB, ENOB$>$9.5) 10-bit SAR ADC working up to 50~MSps and consuming 680~uW@40~MSps. The goal of the new design was to add an internal threshold for the processed input signal, so as to stop the conversion and...
This contribution introduces a novel test system developed to evaluate the signal transmission quality in high-speed data links for the 2026 Inner Tracker upgrade of the ATLAS experiment. Using an FPGA-based data acquisition framework, the setup can run simultaneous Bit Error Rate (BER) tests for many channels and generate virtual eye diagrams, for qualifying the ~26K electrical links of ATLAS...
The CoRDIA X-ray detector is a development targeting experiments at modern diffraction-limited synchrotron rings and free-electron lasers operating either in continuous wave or quasi-continuous long burst modes with photon bunch frequencies up to a few 100kHz. It’s a hybrid detector with sensitive tiles formed by a read-out ASIC bump bonded to a sensor. Since 2020 4 prototype ASICs were...
he TaichuPix chip, a dedicated monolithic pixel sensor for the CEPC vertex detector R&D, demands a raw data rate up to 3.84Gbps and power consumption of less than 25mA/Gbps for the serializer circuit. The TaichuPix1 achieved a maximum data rate of 3.36Gbps with large jitter and current. Subsequently, two 4Gbps serializers were developed and optimized to meet the requirements. Despite...
The High-Luminosity LHC will start operations for physics in 2029.
This expansion of the dataset will be achieved by increasing the number of collisions per bunch crossing, leading to higher radiation doses and busier events. To cope with those harsher conditions and to be compatible with the new ATLAS data acquisition paradigm, the ATLAS Liquid Argon Calorimeter on-detector electronics...
Validation of the recent FPGA firmware logic used in particle physics is being hard, since the implemented logic becomes larger and more complex with increasing FPGA resources. In order to address efficiently, we have developed a firmware validation system using the FPGA accelerator produced by FPGA vendors. We have established a system by developing the interface with CPU of host computer,...
At LHC phase 2, the CMS detector electronics need a precise clock to discriminate piled-up events. The backend electronics of the barrel electromagnetic calorimeter (ECAL) supplies the high-precision clock to the frontend. However, after a reset in the deserializer, the resulting phase of the recovered clock is not accurately repetitive. Therefore we have studied a case where the system...
For nearly 20 years, the Power Supply and Crate Service at CERN has been responsible for the maintenance tracking of power supplies and crates used by the CERN experiments. With this experience, and with the imminent introduction of a new generation of power supplies for the HL-LHC, the timing is opportune to conduct a statistical analysis to draw lessons from the past and make recommendations...
The CBM experiment uses a free streaming DAQ with interaction rates up to 10MHz resulting in data rates, which exceed storage capabilities, necessitating online processing. The SPADIC ASIC of the CBM-TRD provides hit messages with oscilloscope-like sampling of the detector data, encoding valuable information. To speed up data unpacking and free up computing time, feature extraction is moved to...
The FELIX system, initially deployed for ATLAS in LHC Run 3, will evolve for Run 4, serving all subdetectors. The system will consist of 350 servers with new custom PCIe FELIX cards and 200 GbE interfaces, handling data at 1 MHz readout rate for a 4.6 TB/s throughput. The new PCIe cards, featuring an AMD Versal Premium FPGA/SoC and advanced connectivity, run upgraded firmware to decode data...
The design and measurement results of a SoC readout ASIC, called FLAXE, developed for the ECAL-p, the electromagnetic calorimeter at the LUXE experiment are presented. The FLAXE consists of 32 channels with programmable gain front-end, fully differential shaper, and a 10-bit SAR ADC in each channel, working nominally at 20 MSps. Due to a very low bunch crossing rate of 10Hz foreseen for the...
The use of ultra-lightweight flexible Printed Circuit Boards (PCBs) in silicon-based particle detectors was pioneered for the ALICE Inner Tracking System 1 (ITS1) and the STAR tracker in the early 2000s. These PCBs feature thin, flexible interconnections made of µm-scale polyimide (e.g. kapton) and metal (e.g. copper or aluminum), offering low-mass yet with stability of mechanical and...
The contribution will concern the analysis of data provided by Gas Electron Multiplier (GEM) detectors already installed in the Compact Muon Solenoid (CMS) experiment. We will focus on the correlations among the baseline current observed in the High Voltage (HV) system, the background radiation, and the Large Hadron Collider (LHC) beam luminosity. Additionally, an update on the discharge rates...
With the streaming data acquisition scheme planned for the CBM experiment, the quality of event reconstruction depends on the accuracy of clock and time distribution. The Timing and Fast Control (TFC) system ensures that all the readout FPGA boards are aligned in time on the sub-clock and the absolute scales. This is achieved by distributing the time information over an optical link with...
The High-Luminosity upgrade of the LHC (HL-LHC) will triple the proton-proton collision rate, posing challenging requirements for the ATLAS trigger and readout system. A low-latency, FPGA-based hardware trigger for muons in the barrel region will be implemented to identify candidates within 1.7 μs from collisions for further refinement by the Monitored-Drift-Tubes-Trigger-Processor. An...
The Phase-II Upgrade of the LHC will increase its instantaneous luminosity by a factor of 7. At the HL-LHC, the number of proton-proton collisions in one bunch crossing increases significantly, putting more stringent requirements on the LHC detectors electronics.
The ATLAS Liquid Argon calorimeter measures the energy of produced particles produced and feeds the ATLAS trigger to identify...
The High Luminosity Large Hadron Collider (HL-LHC) necessitates a complete replacement of the current Compact Muon Solenoid (CMS) silicon tracker due to harsh conditions. The Phase-2 Outer Tracker (OT) is designed with high radiation tolerance, increased granularity, and enhanced data rate handling. It will provide tracking data to the Level-1 trigger, maintaining sustainable trigger rates...
The data acquisition system of the Micro-Vertex Detector in the PANDA experiment, including the recent advancements in the design of the data concentrator (MDC) ASIC, will be presented. The MDC is a local digital controller on the detector module. The contribution describes the entire readout chain, encompassing the double-side microstrip sensors, the ToASt front-end ASICs, the MDC, the lpGBT...
The high luminosity operation of the LHC will deliver collisions with a luminosity about 10 times the original design value. This poses a big challenge for trigger and data acquisition due to nearly 200 overlapping collisions, called pile up, within the same bunch crossing. Disentanglement of the pileup particles from those of interesting physics processes is achieved by implementing the...
A phase locked loop (PLL) and a time to digital converter (TDC) have been developed for the FastIC+ chip, an 8-channel ASIC to readout fast timing detectors. The chip is designed to work with sensors such as multi-anode photo multipliers (MAPMTs), microchannel plates (MCPs), silicon photomultipliers (SiPMs), among others. The PLL generates the clock reference for the whole chip, including a...
The COLUTA ASIC is an 8-channel, 15-bit, 40 MSPS, analog-to-digital (ADC) converter designed for the high-luminosity LHC (HL-LHC) upgrade of the Liquid Argon calorimeter readout electronics. The production version of the ADC meets and exceeds the specifications for the analog performance and the HL-LHC radiation tolerance. The production testing will be performed by a custom-designed robotic...
Based on the fourth generation synchrotron radiation light source, the stability of X-ray beam is an urgent problem to be solved in current cutting-edge experiments. This project is based on fast response time of diamond detectors. A fast response four channel weak current measurement and data acquisition circuit based on diamond detectors was developed using ADA4530. Experimental tests show...
Verification is a critical aspect of designing Front-end (FE) readout ASICs for High-Energy Physics (HEP) experiments. These ASICs share several similar functional features, resulting in similar verification objectives, which can be addressed using comparable verification strategies. This contribution presents a set of re-usable verification components for addressing common verification tasks,...
Special considerations have been made in the design to reduce digital state changes and ensure reliable operation, we tested the effectiveness of the protection by running separate chips inside the proton beam, and layout is that all chips concurrently fit into a 20 mm beam spot. The
study of corrected bit flips in registers and actual SEEs in LCB and LP path is carried out under different...
Monolithic active pixel sensors are considered as the nominal choice for a large variety of particle physics experiments. Consequently, the design of pixel matrices faces a wide range of specifications.
We developed a pixel matrix read-out architecture based on the local interconnection of asynchronous N:1 time arbiters with fixed priority. This architecture is not limited by global signals...
In preparation for the High-Luminosity-Upgrade of the Large Hadron Collider, new silicon strip detector modules need to be built for the ATLAS ITk strip tracker. The powerboard flexes in ITk strip modules are responsible for powering all readout electronics as well as controlling and monitoring module voltages, currents and temperatures. In total, about 6000 end-cap powerboards need to be...
To mitigate the impacts of pileup caused by luminosity increase in the ATLAS Phase-II upgrade, the High Granularity Timing Detector (HGTD) is proposed to measure the timing of tracks precisely. The Peripheral Electronics Board (PEB) is an important part of the HGTD, which acts as a bridge between the front-end modules and the off-detector electronics. We have designed and produced a prototype...
The COMET (COherent Muon to Electron Transition) experiment at J-PARC requires particle detectors on the beam axis for proton and muon-pion flux monitoring. The GAROP-2 (GAted-ReadOut Proton 2) is thus dedicatedly developed as the read-out electronics for the diamond or SiC monitors. The detectors and GAROP-2 are gated off at the proton pulse phase to prevent it from saturation. Added to this...
After Run III the ATLAS detector will undergo many upgrades to cope with the harsher radiation environment and increased number of proton interactions in the high luminosity phase of the LHC. One key project of this upgrade is the ATLAS Inner Tracker (ITk). The pixel detector of the ITk must be read out at 1,28Gb/s with a BER at 95%CL less than 10^-12. The Optosystem performs opto-electrical...
The HGTD is a novel detector introduced to augment the new all-silicon Inner Tracker in the pseudo-rapidity range from 2.4 to 4.0, adding the capability to measure charged-particle trajectories in time as well as space. A prototype of Peripheral Electronics Board (PEB), which supports up to 55 front-end modules with 12 lpGBT, 9 VTRx+ and 52 bPOL12v, is developed to work as a bridge between the...
Resistive Plate Chambers (RPCs) are versatile detectors widely used in HEP experiments due to their excellent timing resolution and efficiency. However, conventional gas mixtures used in RPCs include C2H2F4 and SF6, freon-based gas mixtures with high global warming potential (GWP). So, a transition to eco-friendly gas is necessary to reduce the environmental impact and long-term operation of...
This work focuses on Total Ionizing Dose (TID) test of LVDS receivers that will be used for the readout system of the ATLAS muon barrel spectrometer within the High Luminosity (HL)-LHC program. We designed an experimental setup that allows to investigate TID effects on power consumption and signal integrity, including variations in amplitude, rise/fall time, jitter, signal-to-noise ratio, as...
The High Luminosity LHC upgrade requires a full revamp of CMS Drift Tubes (DT) electronics due to trigger rates exceeding current capabilities. Leveraging optical and bandwidth advancements, this upgrade redefines DT electronics architecture. On-detector functions are streamlined for data processing relocation to a more accessible back-end. The On-detector Board for Drift Tubes (OBDT) is...
This contribution presents the methodology and verification strategy for OBELIX, the monolithic active pixel CMOS sensor designed for the proposed upgrade of the Belle II vertex detector. Leveraging a dual verification approach with cocotb and UVM, we ensure the integrity of OBELIX's digital logic. This methodology addresses the complexities of ASIC design, which includes an 896x464 pixel...
