Speaker
Description
Non-Human Primates (NHPs) are central to neuroscience research due to their complex behavioral interactions and physiological similarities to the human brain. A principal motivation behind the NHP research in the aoLab at the University of Washington is to understand and model neural circuits, which can be translated for practical applications for humans. However, the nonlinear interconnections within the brain challenge the isolation and study of specific neuronal structures during experiments, necessitating real-time stimulation of those regions.
Modern CPUs and GPUs cannot meet the millisecond-order latency constraint for real-time brain stimulation, in which the incoming data must be processed, passed through a mathematical model of the region, and encoded into stimulation patterns. To address this bottleneck, we integrate Field Programmable Gate Arrays (FPGAs) within an existing experimental apparatus using Neuropixels probes to collect spiking data from 300+ electrode channels. Additionally, we use the Latent Factor Analysis via Dynamical Systems (LFADS) architecture based on a sequential Variational Autoencoder (VAE) to model the dynamics of the brain region and predict future firing activity during experimentation.
Typically, passing a single batch of data (Channels x TimeSteps) for inference through LFADS requires 30.42ms on an Intel i7 CPU and 28.8ms on an NVIDIA A4000 GPU; exceeding the millisecond-order timeline of a single spike. The same process requires only 0.65ms on a Xilinx U55C FPGA, enabling the system to respond to inferred spike activity by stimulating the region. This gap in performance widens significantly with larger batches due to the multi-staged processing pipeline in the FPGA. However, the LFADS model weights were quantized due to limited hardware resources on the FPGA, reducing model accuracy from 91.3% for the full floating-point variant to 80.2% on test data. Even so, the system provides a platform to deploy and test hypotheses of functional and behavioral attributes of neuronal circuits by leveraging hardware acceleration.
