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BI/TB: SoM specifications' review
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Europe/Zurich
866/2-D05 (CERN)
BI/TB: SoM specifications' review
Manoel Presented the specifications collected from the stakeholders in BI and in EPC.
- The type and size of external memory seems to be the only point of divergence: EPC might need a SRAM while BI would need DDR <= Action on Manoel to clarify the actual needs and confirm it is not a critical point given the FPGA's intternal memory size
- The power dissipation is a conccern: EPC measured 70+ degrees on the DI/OT system board even using forced convection helped by a fan <= Action on Manoel to follow up and report on the tests performed by EPC
- For the connectors EPC proposed the use of FMC ones given the high density and compatibility with high speed communication
- The SoM shall follow the indications and guidelines resulting from the CTTB SoC task force
- The DI/OT system board is the starting point for the design of the SoM
- the board should be analysed and cost driving components/blocks not part of the specifications should be excluded <= Action on Kiran
- the SoC taskforce identified some elements to be standardised: those parts should be added as part of the requirements <= action on Manoel
- It was pointed out that some application in the future might profit of a GPU, but having it on the SoM was ruled out:
- adding an external GPU would be expensive also in terms of real estate and heat dissipation
- the PL can be used to accelerate the processing
- a GPU could be added to the carrier of the applications requiring it
- The use of a SoM allows the customisation of the periferals to the specific need of the projects, nevertheless this should not lead to the proliferation of platform standards: each project should present in the same TB how they see the SoM integrated in their back-end <= action on the SL to collect those infos and on Andrea to organise the TB
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