Choose timezone
Your profile timezone:
HGTD Interlock System
→
Europe/Zurich
,
Description
discuss HGTD interlocking for HV power supply
Interface DCS, MBIS, MIC
Videoconference
ITk Interlock System
- Zoom Meeting ID
- 64731058797
- Description
- ATLAS safety ; interlock system for ITk, HGTD,.... monitoring temperature, ON/OFF HV and LV Power supply detector LISSY Crate / MIC Crate
- Host
- Cyril Drancourt
- Useful links
- Join via phone
- Zoom URL
-
"DCS READY" flag cannot be used because Mon-FPGA and EMP/OPC circuit is
for monitoring purposes only.
HVP (High Voltage Present) signal plays a crucial role in the interface
between HV Power supplies and LHC/BIS system. There is no way to play around it.
Nick wants a block diagram with the logic of the DCS signal. It is
important to keep in mind that DCS cannot provide status of individual
HV PS. DCS can only provide IP (Injection Permit) independently of the
actual HV PS states.
HV value should be generated in HV crates. Drawback is that if there is a DCS reading error (digital error) we do not know the actual state
BIS card could, in principle, be used to propagate "non-SB" (stable beam)
flag, and, so, shutdown (reduce) HV but we need to provide feedback to
LHC, confirming that the HV are off. How to do this? (again we we need a
hardware signal with HV status).
There are minutes attached to this event.
Show them.
