Speaker
Description
Silicon tracking detectors in future high energy physics experiments usually requires excellent spatial resolution, nanosecond level timing resolution, good radiation hardness and large area coverage. High-Voltage CMOS sensors, exploiting commercial CMOS technologies, are intrinsically radiation hard and cost-effective for use in large quantities. With successful development in 180nm and 150nm processes, HVCMOS has become promising technical candidates for experiments like CEPC and LHCb upgrade. To achieve better spatial resolution, more functionality and lower power consumption, deveopment of HVCMOS in sub-100nm process is being explored. This talk will present the design and preliminary test of COFFEE2 chip, the first HVCMOS prototype in 55nm process. The IV and CV curves are tested using a small array of passive sensor diodes, and a breakdown voltage of -70V is reached for a regular low-resistivity wafer. Pixels with a variety of in-pixel circuits are designed, with amplifiers and comparators. Signal responses are observed for laser and radioactive sources. Plans of future R&D will also be briefly discussed.
