Speaker
Description
The release of the Timepix4 [1] readout chip has opened new possibilities for the utilization of pixel detectors in experimental applications. With its exceptional time resolution (binning approximately 200 ps), larger detection area (512x448 pixels), and extremely high maximum data rate (160 Gbps), it is evident that the scientific community has gained a powerful new tool.
In this contribution, we discuss the challenges associated with designing instrumentation for Timepix4. We introduce the concept of the planned readout system for this detector and, more specifically, present the designed chipboards for Timepix4. These chipboards, compared to previous designs, are fundamental to achieving high-quality measurement results. The authors introduce two solutions for Timepix4: the first is a single-chip board carrier, and the second adopts a modular approach to detector chipboard design. The system is divided into two distinct components: the sensor module and the mainboard. This separation enhances flexibility, versatility, and ease of use while maintaining high performance and measurement accuracy.
The sensor module is built around the Timepix4 chip, which is bonded to the module and optimized for high-speed data transfer and signal integrity. Operating without active components aside from the chip itself, the module ensures simplicity and reliability. It features high-speed inter-board connectors (up to 40 Gbps), enabling data throughput of approximately 600 MHit/s. The modular design supports the integration of various sensor types and the construction of large-area detector systems.
The mainboard serves as the power and signal interface for the sensor module. It supplies the necessary voltage levels for the Timepix4 chip, employing a dual-stage power supply topology to ensure low noise and high stability. The mainboard also manages signal routing between the sensor module and the readout electronics, achieving a maximum data transfer rate of 5 Gbps per differential pair. The readout system is connected via four RJ45 connectors, offering flexible user setup configurations.
Initial tests conducted at the CERN SPS facility demonstrated (results will be presented) the detector's functionality and validated the design's technical feasibility. The modular architecture and scalable design of this system present promising applications for a wide range of high-performance particle detection setups.
References:
[1] X. Llopart et al 2022 JINST 17 C01044
