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09:00
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Welcome
-
Alessandro Caratelli
(CERN)
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09:20
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SystemVerilog accelerated verification using UVM
-
Luca Brambilla
(Cadence)
(until 10:30)
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10:30
|
--- Coffee break ---
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|
10:45
|
SystemVerilog accelerated verification using UVM
-
Luca Brambilla
(Cadence)
(until 12:00)
|
|
|
09:00
|
SystemVerilog accelerated verification using UVM
-
Luca Brambilla
(Cadence)
(until 10:30)
|
|
10:30
|
--- Coffee break ---
|
|
10:45
|
SystemVerilog accelerated verification using UVM
-
Luca Brambilla
(Cadence)
(until 12:00)
|
|
|
09:00
|
SystemVerilog accelerated verification using UVM
-
Luca Brambilla
(Cadence)
(until 10:30)
|
|
10:30
|
--- Coffee break ---
|
|
10:45
|
SystemVerilog accelerated verification using UVM
-
Luca Brambilla
(Cadence)
(until 12:00)
|
|
|
09:00
|
Verification best practices for HEP
(until 10:30)
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10:30
|
--- Coffee break ---
|
|
10:45
|
Verification best practices for HEP
(until 12:00)
|
|
|
12:00
|
--- Lunch break ---
|
|
13:00
|
SystemVerilog accelerated verification using UVM
-
Luca Brambilla
(Cadence)
(until 15:15)
|
|
15:15
|
--- Coffee break ---
|
|
15:30
|
SystemVerilog accelerated verification using UVM
-
Luca Brambilla
(Cadence)
(until 17:30)
|
|
|
12:00
|
--- Lunch break ---
|
|
13:00
|
SystemVerilog accelerated verification using UVM
-
Luca Brambilla
(Cadence)
(until 15:15)
|
|
15:15
|
--- Coffee break ---
|
|
15:30
|
SystemVerilog accelerated verification using UVM
-
Luca Brambilla
(Cadence)
(until 17:30)
|
|
|
12:00
|
--- Lunch break ---
|
|
13:00
|
SystemVerilog accelerated verification using UVM
-
Luca Brambilla
(Cadence)
(until 15:15)
|
|
15:15
|
--- Coffee break ---
|
|
15:30
|
SystemVerilog accelerated verification using UVM
-
Luca Brambilla
(Cadence)
(until 17:30)
|
|
|
12:00
|
--- Lunch break ---
|
|
13:00
|
Verification best practices for HEP
(until 15:15)
|
|
15:15
|
--- Coffee break ---
|
|
15:30
|
Verification best practices for HEP
(until 17:30)
|
|
