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Verification with UVM for HEP Workshop

→ Europe/Zurich
593/R-013 (CERN)

593/R-013

CERN

10
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Adithya Pulli (CERN), Alessandro Caratelli (CERN), Marco Andorno (CERN), Matteo Lupi (CERN), Simone Scarfi' (CERN)
Description

CERN ASIC Support and Foundry Services

Welcome.pdf
Module 1
MODULE 2
CERN ASIC Support
Registration
Registration
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Verification with UVM for HEP Workshop - Module 2
Zoom Meeting ID
68891259663
Host
Alessandro Caratelli
Alternative host
Adithya Pulli
Passcode
65880810
Useful links
Join via phone
Zoom URL
  • Monday 25 November
    • 09:00 → 09:20
      Welcome 20m
      Speaker: Alessandro Caratelli (CERN)
    • 09:20 → 10:30
      SystemVerilog accelerated verification using UVM
      Convener: Luca Brambilla (Cadence)
    • 10:30 → 10:45
      Coffee break 15m
    • 10:45 → 12:00
      SystemVerilog accelerated verification using UVM
      Convener: Luca Brambilla (Cadence)
    • 12:00 → 13:00
      Lunch break 1h
    • 13:00 → 15:15
      SystemVerilog accelerated verification using UVM
      Convener: Luca Brambilla (Cadence)
    • 15:15 → 15:30
      Coffee break 15m
    • 15:30 → 17:30
      SystemVerilog accelerated verification using UVM
      Convener: Luca Brambilla (Cadence)
  • Tuesday 26 November
    • 09:00 → 10:30
      SystemVerilog accelerated verification using UVM
      Convener: Luca Brambilla (Cadence)
    • 10:30 → 10:45
      Coffee break 15m
    • 10:45 → 12:00
      SystemVerilog accelerated verification using UVM
      Convener: Luca Brambilla (Cadence)
    • 12:00 → 13:00
      Lunch break 1h
    • 13:00 → 15:15
      SystemVerilog accelerated verification using UVM
      Convener: Luca Brambilla (Cadence)
    • 15:15 → 15:30
      Coffee break 15m
    • 15:30 → 17:30
      SystemVerilog accelerated verification using UVM
      Convener: Luca Brambilla (Cadence)
  • Wednesday 27 November
    • 09:00 → 10:30
      SystemVerilog accelerated verification using UVM
      Convener: Luca Brambilla (Cadence)
    • 10:30 → 10:45
      Coffee break 15m
    • 10:45 → 12:00
      SystemVerilog accelerated verification using UVM
      Convener: Luca Brambilla (Cadence)
    • 12:00 → 13:00
      Lunch break 1h
    • 13:00 → 15:15
      SystemVerilog accelerated verification using UVM
      Convener: Luca Brambilla (Cadence)
    • 15:15 → 15:30
      Coffee break 15m
    • 15:30 → 17:30
      SystemVerilog accelerated verification using UVM
      Convener: Luca Brambilla (Cadence)
  • Thursday 28 November
    • 09:00 → 10:30
      Verification best practices for HEP
    • 10:30 → 10:45
      Coffee break 15m
    • 10:45 → 12:00
      Verification best practices for HEP
    • 12:00 → 13:00
      Lunch break 1h
    • 13:00 → 15:15
      Verification best practices for HEP
    • 15:15 → 15:30
      Coffee break 15m
    • 15:30 → 17:30
      Verification best practices for HEP
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