Speaker
Jovan Mitrevski
(Fermi National Accelerator Lab. (US))
Description
Since version 1.0, hls4ml has provided a oneAPI backend for Altera FPGAs, as an evolution of the backend that targeted Intel HLS. Some design choices will be presented here, including the use of pipes and task sequences to develop a dataflow-style architecture. The oneAPI framework, unlike the Intel HLS framework, also naturally supports an accelerator-style deployment. Using always-run kernels and DMA transfers, we can efficiently deploy neural networks in hardware in an accelerator style, which we will describe.
Authors
Enrico Lupi
(CERN, INFN Padova (IT))
Harry Wang
(Altera Corporation)
Jovan Mitrevski
(Fermi National Accelerator Lab. (US))
Lauri Antti Olavi Laatu
(Imperial College (GB))
Paul White
(Altera Corporation)
Suleyman Demirsoy
(Altera Corporation)
Vladimir Loncar
(CERN)