1–5 Sept 2025
ETH Zurich
Europe/Zurich timezone

High Throughput FPGA Deployment of Distilled Deep Sets Networks for Jet Preselection in the High-Level Trigger

Not scheduled
20m
HIT G floor (gallery)

HIT G floor (gallery)

Speakers

ATLAS TDAQ collaboration Lucas Bezio (Universite de Geneve (CH))

Description

Deep Sets-based neural networks are well-suited to learning from unordered, variable-length inputs such as particle tracks associated with jets. Their permutation-invariant structure makes them attractive for high-energy physics (HEP) applications where input ordering is ambiguous and throughput is a critical constraint. In this work, we explore the use of such architectures on Field-Programmable Gate Arrays (FPGAs) to enable fast and resource-efficient inference within the High-Level Trigger (HLT), where track-level features become available and event processing must be optimized for rate rather than latency.

We build on the DIPS (Deep Impact Parameter Sets) algorithm, a Deep Sets-based flavour-tagging model previously used in ATLAS, and adapt it for quantization-aware training and efficient FPGA implementation using QKeras and hls4ml. To maximize throughput without sacrificing classification performance, we introduce knowledge distillation: a high-capacity teacher network guides the training of a compact student model optimized for FPGA deployment. This approach allows us to retain strong discriminative power while drastically reducing inference cost.

Our implementation demonstrates that Deep Sets networks can be effectively mapped to FPGA hardware, including mechanisms for handling variable-length, permutation-invariant inputs. We report detailed results from real FPGA deployments, including resource usage, measured latency, and especially sustained throughput under different configurations.

Rather than competing directly with more sophisticated architectures such as graph neural networks (GNNs), our goal is to provide a high-throughput preselection stage that can reduce the number of events requiring costly downstream inference. In doing so, we enable a more efficient use of compute resources in the HLT pipeline, providing early rejection capabilities with minimal impact on tagging performance.

This work highlights a complementary strategy for deploying ML on FPGAs in HEP: prioritizing throughput to enable scalable inference pipelines and alleviate computational bottlenecks, especially in data-rich environments such as the upgraded ATLAS trigger.

Authors

ATLAS TDAQ collaboration Lucas Bezio (Universite de Geneve (CH))

Presentation materials