Speakers
Description
This tutorial explores the growing demand for domain-specific hardware accelerators driven by the rapid evolution of AI and data analytics. Traditional hardware design cycles are too slow to keep up with the pace of algorithmic innovation. To address this, new agile hardware design methodologies are emerging, leveraging compiler technologies and High-Level Synthesis (HLS) to automate and accelerate the design process.
The tutorial introduces the SODA Synthesizer, an open-source, compiler-based toolchain that enables the generation of efficient hardware accelerators from high-level algorithm descriptions.
It consists of:
- SODA-OPT: A front-end and optimizer built on the MLIR (Multi-Level Intermediate Representation) framework. It interfaces with popular Python-based data science and machine learning frameworks, performing hardware/software partitioning and domain-specific optimizations.
- Bambu: A state-of-the-art open-source HLS tool developed at Politecnico di Milano. It translates optimized high-level code into hardware designs, supporting both FPGA and ASIC targets, and integrates with RTL simulation and logic synthesis tools.
The tutorial highlights the limitations of traditional HLS tools, which were primarily designed for digital signal processing and required expertise in hardware description languages (HDLs). Modern HLS tools now support parallel programming models and integrate with high-level frameworks, making them more accessible to software developers and domain scientists.
Key topics include:
- Current trends and methodologies in agile hardware design.
- Advantages and limitations of conventional HLS approaches.
- The role of MLIR in supporting diverse domains and frameworks.
- Hands-on demonstrations of both SODA-OPT and Bambu, showing how to go from Python code to optimized hardware accelerators.
The tutorial also demonstrates how the toolchain integrates with both commercial and open-source Electronic Design Automation (EDA) tools, such as OpenROAD, enabling a complete end-to-end flow from Python to silicon. The design flow is flexible and supports both FPGA prototyping and ASIC implementation, making it suitable for a wide range of applications in AI and data-intensive computing.
This tutorial is intended for researchers, engineers, and developers interested in accelerating AI and data-driven applications through agile hardware design, even without deep expertise in traditional hardware design languages.
References
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[1] G. Gozzi, M. Fiorito, S. Curzel, C. Barone, V. G. Castellana, M. Minutoli, A. Tumeo, and F. Ferrandi: SPARTA: High-Level Synthesis of Parallel Multi-Threaded Accelerators. ACM Trans. Reconfigurable Technol. Syst. 18, 1, Article 9 (March 2025).
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[2] N. Bohm Agostini, S. Curzel, J. Zhang, A. Limaye, C. Tan, V. Amatya, M. Minutoli, V. G. Castellana, J. B. Manzano, D. Brooks, G-Y. Wei, A. Tumeo: Bridging Python to Silicon: The SODA Toolchain. IEEE Micro 42(5): 78-88 (2022) (Best paper for 2022)
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[3] N. Bohm Agostini, S. Curzel, V. Amatya, C. Tan, M. Minutoli, V. G. Castellana, J. B. Manzano, D. R. Kaeli, A. Tumeo: An MLIR-based Compiler Flow for System-Level Design and Hardware Acceleration. ICCAD 2022: 6:1-6:9
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[4] F. Ferrandi, V. G. Castellana, S. Curzel, P. Fezzardi, M. Fiorito, M. Lattuada, M. Minutoli, C. Pilato, A. Tumeo: Invited: Bambu: an Open-Source Research Framework for the High-Level Synthesis of Complex Applications. DAC 2021: 1327-1330