Fast Machine Learning for Science Conference 2025

Session

Tutorials

1 Sept 2025, 09:00

ETH Zurich

1. hls4ml

Benjamin Ramhorst (ETH Zurich)

01/09/2025, 09:00

Tutorials

Tutorial

FPGAs provide unique advantages in the realm of machine learning acceleration. Unlike CPUs and GPUs, FPGAs allow for custom parallelism, data type precision and dataflow tailored specifically to the workload. Their reconfigurability enables the design of optimised hardware circuits that can reduce latency, power consumption, and improve throughput. Some common examples of FPGA-accelerated...

72. NeuraLUT-Assemble: Hardware-aware Assembling of Sub-Neural Networks for Efficient LUT Inference

Marta Andronic (Imperial College London), Mr Oliver Cassidy (Imperial College London)

01/09/2025, 09:00

Tutorial

Neural networks (NNs) have gained significant interest in recent years due to their prevalence in AI applications. Lookup table (LUT) based NN architectures have emerged as a promising solution for ultra-low latency inference on reconfigurable hardware such as field programmable gate arrays (FPGAs). These techniques promise significant enhancements in both resource efficiency and inference...

123. Part 1: Agile Hardware Design for AI: A Hands-On Tutorial with SODA and Bambu

Mr Giovanni Gozzi (Politecnico di Milano), Mr Michele Fiorito (Politecnico di Milano), Dr Vito Giovanni Castellana (Pacific Northwest National Laboratory), Dr Antonino Tumeo (Pacific Northwest National Laboratory), Fabrizio Ferrandi (Politecnico di Milano)

01/09/2025, 09:00

Tutorial

This tutorial explores the growing demand for domain-specific hardware accelerators driven by the rapid evolution of AI and data analytics. Traditional hardware design cycles are too slow to keep up with the pace of algorithmic innovation. To address this, new agile hardware design methodologies are emerging, leveraging compiler technologies and High-Level Synthesis (HLS) to automate and...

18. Coyote v2: Open-source Abstractions and Infrastructure for FPGAs

Benjamin Ramhorst (ETH Zurich)

01/09/2025, 11:00

Tutorial

As Moore’s Law and Dennard Scaling reach their limits, computing is shifting toward heterogeneous hardware for large-scale data processing. Cloud vendors are deploying accelerators, like GPUs, DPUs, and FPGAs, to meet growing computational demands of ML and big data.

While FPGAs offer great flexibility and performance, practically integrating them in larger systems remains challenging due...

53. Designing and Deploying Low-Latency Neural Networks on FPGAs with HGQ and da4ml

Chang Sun (California Institute of Technology (US))

01/09/2025, 11:00

Tutorials

Tutorial

Neural networks with a latency requirement on the order of microseconds are widely used at the CERN Large Hadron Collider, particularly in the low-level trigger system. To satisfy this latency requirement, these neural networks are often deployed on FPGAs.

This tutorial aims to provide a practical, hands-on guide of a software-hardware co-design workflow using the HGQ2 and da4ml libraries....

153. Part 2: Agile Hardware Design for AI: A Hands-On Tutorial with SODA and Bambu

Mr Giovanni Gozzi (Politecnico di Milano), Mr Michele Fiorito (Politecnico di Milano), Dr Vito Giovanni Castellana (Pacific Northwest National Laboratory), Dr Antonino Tumeo (Pacific Northwest National Laboratory), Fabrizio Ferrandi (Politecnico di Milano), Nicolo Ghielmetti (CERN)

01/09/2025, 11:00

Tutorial

This tutorial explores the growing demand for domain-specific hardware accelerators driven by the rapid evolution of AI and data analytics. Traditional hardware design cycles are too slow to keep up with the pace of algorithmic innovation. To address this, new agile hardware design methodologies are emerging, leveraging compiler technologies and High-Level Synthesis (HLS) to automate and...

82. Super Neural Architecture Codesign Package (SNAC-Pack)

Dmitri Demler

01/09/2025, 11:00

Tutorial

Machine learning has become a critical tool for analysis and decision-making across a wide range of scientific domains, from particle physics to materials science. However, the deployment of neural networks in resource-constrained environments, such as hardware accelerators and edge devices, remains a significant challenge. This often requires specialized expertise in both neural architecture...

5. Coyote v2: Open-source Abstractions and Infrastructure for FPGAs

Benjamin Ramhorst (ETH Zurich), Gustavo Alonso (ETH Zurich), Maximilian Jakob Heer (ETH Zurich)

Tutorials

Authors:
Gustavo Alonso, Maximilian Jakob Heer, Benjamin Ramhorst
As Moore’s Law and Dennard Scaling reach their limits, computing is shifting toward heterogeneous hardware for large-scale data processing. Cloud vendors are deploying accelerators, like GPUs, DPUs, and FPGAs, to meet growing computational demands of ML and big data.

While FPGAs offer great flexibility and performance,...

3. hls4ml tutorial

Benjamin Ramhorst (ETH Zurich)

Tutorials

In this tutorial, you will get familiar with the hls4ml library. This library converts pre-trained Machine Learning models into FPGA firmware, targeting extreme low-latency inference. You will learn techniques for model compression, including how to reduce the footprint of your model using state-of-the-art techniques such as quantization. Finally, you will learn how to synthesize your model...

4. Tutorial 2

6. Tutorial 4

7. Tutorial 5

8. Tutorial 6