Speaker
Description
Caribou is a versatile data acquisition system used in multiple collaborative frameworks (CERN EP R&D, DRD3, AIDAinnova, Tangerine) for laboratory and test-beam qualification of novel silicon pixel detector prototypes. The system is built around a common hardware, firmware and software stack shared across different projects, thereby drastically reducing the development effort and cost. It consists of a custom Control and Readout (CaR) board and a commercial AMD Zynq System-on-Chip (SoC) platform. The SoC runs a Yocto distribution integrating the custom software framework (Peary) and custom FPGA firmware built within a common firmware infrastructure (Boreal). The CaR board provides a hardware environment providing various resources such as power supplies, slow control interfaces, and high-speed data links for the target detector prototype. Boreal and Peary, in turn, offer firmware and software environments that enable seamless integration of control and readout for new detector prototypes. Additionally, a unified testing method, integrated into the above frameworks that supports the FPGA device families in use, is currently under development. While the first version of the system used a SoC platform based on the ZC706 evaluation board, migration to Zynq UltraScale+ platforms is progressing with the finalized support of the ZCU102 board and the ultimate objective of integrating the SoC functionality directly into the CaR board, eliminating the need for separate evaluation boards. This talk describes the Caribou system, focusing on the latest project developments and showcasing progress and future plans across its hardware, firmware, and software components.
| Type of presentation (in-person/online) | in-person presentation |
|---|---|
| Type of presentation (I. scientific results or II. project proposal) | I. Presentation on scientific results |
