3rd DRD3 week on Solid State Detectors R&D

Session

WG/WP1 - CMOS technologies

2 Jun 2025, 14:20

Nikhef, Amsterdam

90. Introduction to WG1/WP1 session

Eva Vilella Figueras (University of Liverpool (GB)), Heinz Pernegger (CERN), Ingrid-Maria Gregor (DESY & Bonn University), Jerome Baudot (IPHC - Strasbourg)

02/06/2025, 14:25

72. Conceptual Basis for Canadian Participation in the MALTA Project: toward a Design and Verification Strategy

Leonard McEchern (Carleton University), Manoj Sachdev (University of Waterloo), Thomas Koffas (Carleton University (CA))

02/06/2025, 14:30

WG1 - Monolithic Sensors

A consortium of Canadian researchers from Carleton and Waterloo Universities has joined the CERN-led MALTA project, a CMOS MAPS project fabricated in the 180nm TowerJazz technology node. We expect that Canadian expertise in analog mixed-signal design, Radiation Hardening by Design (RHBD) and algorithmic error correction for hardware implementation will be particularly valuable in advancing the...

57. The first prototype Monolithic Active Pixel Sensor for The OCTOPUS Project

Fadoua Guezzi Messaoud (Centre National de la Recherche Scientifique (FR))

02/06/2025, 15:00

WG1 - Monolithic Sensors

The First Monolithic Active Pixel Sensor Prototype for The OCTOPUS Project

Fadoua Guezzi Messaoud on behalf of the OCTOPUS project
Institut Pluridisciplinaire Hubert Curien IPHC, Strasbourg, France
Email: fadoua.guezzi-messaoud@iphc.cnrs.fr

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Abstract

The next generation of lepton colliders will require extremely...

62. The Versatile MAPS project

Michael Deveaux (GSI - Helmholtzzentrum fur Schwerionenforschung GmbH (DE))

02/06/2025, 15:35

WG1 - Monolithic Sensors

The Versatile MAPS project was started in response to the needs of several collaborations for a high performance ultra-low power MAPS detector for tracking applications. While there is a common understanding on the spatial precision (about 10 µm) and on a thinning of the sensors to the typical thickness (50 µm), the requirements in terms of rate capability, power and time stamping vary...

89. 1 ns to 100 ps timing precision architecture (PMaTT) in TPSCo 65nm with Update on NAPA and TDC @ SLAC

Caterina Vernieri (SLAC National Accelerator Laboratory (US)), Didier Claude Contardo (Centre National de la Recherche Scientifique (FR))

02/06/2025, 16:30

41. Status of the non amplified MiniCactus V2 chip in LF15A technology and first steps towards sensors with intrinsic amplification.

Prof. Philippe Schwemling (Université Paris-Saclay (FR)), Yavuz Degerli (CEA Saclay)

02/06/2025, 17:00

WG1 - Monolithic Sensors

The Cactus and MiniCactus chip series are demonstrator sensors optimized for precision time measurement of the time of arrival of charged particles. Their goal is to explore the performance that can be obtained from non amplified monolithic sensors, especially with the LFoundry LF15A 150 nm technology. The last iteration of MiniCactus, called MiniCactus V2, has been tested in beam in June-July...

85. Monolithic strip sensors

Ingrid-Maria Gregor (DESY & Bonn University)

02/06/2025, 17:30

34. HV-CMOS Pixel Detector Demonstrator with Serial Powering and Innovative Interconnections

Prof. Attilio Andreazza (Università degli Studi e INFN Milano (IT))

03/06/2025, 09:00

WG1 - Monolithic Sensors

This Common Project proposal aims to develop a HV-CMOS multi-chip pixel detector demonstrator suitable for large scale production in future Higgs factory experiments, based on multi-chip modules with data aggregation and serial powering capabilities. These multi-chip modules, including low-mass multilayer flexible PCBs, will then be integrated in staves, where modules will be powered in...

44. All-silicon ladder concept for CMOS monolithic pixel detectors

Nana Chychkalo (Georg August Universitaet Goettingen (DE))

03/06/2025, 09:30

WG1 - Monolithic Sensors

The All-Silicon project focuses on the development of monolithic CMOS pixel modules. Unlike traditional pixel detector modules, which involve individually diced chips from the wafer that are subsequently glued onto a support structure, the all-silicon approach integrates several CMOS chips into a single, uniform ladder, cut from a single silicon wafer. Each ladder is diced in one large...

58. Design and characterization of CASSIA monolithic pixel sensors with gain

Ivan Berdalovic, Tomislav Suligoj (University of Zagreb - FER)

03/06/2025, 10:00

WG1 - Monolithic Sensors

The CASSIA (CMOS Active SenSor with Internal Amplification) project is focused on developing monolithic active pixel sensors (MAPS) with internal signal gain in a commercial CMOS technology. The advantages of this approach include a higher input signal enabling simplification of in-pixel electronics, an improved signal-to-noise ratio for radiation hardness, and superior timing resolution for...

22. Design of COFFEE3, a small prototype for 55nm HVCMOS validation

Dr Yang Zhou (Institute of High Energy Physics, CAS, Beijing, China)

03/06/2025, 11:00

WG1 - Monolithic Sensors

The HVCMOS technology is promising technology for tracking detectors at future experiments such as LHCb upgrade and Higgs factories, for its radiation hardness, fast charge collection and hence good spatial and timing resolution. Development of HVCMOS in smaller feature size will allow more functionailities in the same pixel area, and a reduced power consumption. We proposed a project to...

60. Towards an OpenSource DMAPS project proposal

Daniel Muenstermann (Lancaster University (GB))

03/06/2025, 11:30

WG1 - Monolithic Sensors

Geopolitics suggest to consider technologies that Europe has full control of. One option to avoid sources that might potentially become unavailable is to focus on Open-Source chip design tools and processes that are hosted in Europe and provide OpenPDKs. While this has already been proven to work for fully digital workflows, there is still a lot of work to be done for mixed-signal chips in...

10. Radiation hard readout architectures

Carlos Solans Sanchez (CERN)

WG1 - Monolithic Sensors

This project proposal aims to develop radiation hard read-out architectures for hit rates above 100~MHz/cm$^{2}$ in Tower semiconductor compatible with HEP experiment services for the HL-LHC and beyond with a trigger-less approach for matrix sizes larger or equal to 2$\times$2~cm$^{2}$, where time tagging of events with sub-bunch crossing resolution is crucial to contribute to physics...