Joint ECF & RAWG Meeting: Reliable Gateware

Thursday 13 Feb 2025, 09:00 → 10:50 Europe/Zurich

774/1-079 (CERN)

09:05 → 09:10 Introduction

Speaker: Mathieu Saccani (CERN)

09:10 → 09:25 HSE/RP

Reliability is crucial for safety-critical systems like CROME. In this presentation, I’ll walk through the different methods our team uses to keep our gateware code as bug-free as possible. We’ll cover directed tests, Python/HDL co-simulation, formal verification, and full HW/SW co-simulation—discussing their strengths, weaknesses, and what works best for a small teams such as ours at CERN.

Speaker: Clyde Laforge (CERN)

09:30 → 09:45 TE/MPE

Development flow and tools on an example project
Focus on Standard IEC62566

Speaker: Antoine Colinet (CERN)

09:50 → 10:05 SY/EPC

Development flow and tools on an example project
Focus on the methodology used in EPC (example project)

Speakers: Adrian Byszuk (CERN), Valerio Nappi

10:10 → 10:25 SY/BI

Gateware verification flow for the BLM LHC processing FPGA
Focus on tools (CI, linter, cheby, VUNIT, HDLmake, script for requirement, documentation…)

Speaker: Konstantinos Blantos

10:30 → 10:50 Discussion