Speaker
Description
The FELIX readout system for the ATLAS experiment has been introduced in the
LHC Run 3. The high granularity timing detector (HGTD) imposes strict timing
requirements that pose significant challenges to the timing distribution
performance expected from the FELIX card FLX-155, equipped with AMD Versal
Premium VP1552 FPGAs. This novel FPGA technology requires a careful scrutiny of
the clock recovery techniques required in conjunction with timing distribution
to the front-end electronics. To address this issue, an efficient solution
called Knypaegje was developed. This algorithm leverages the ARM processor
within the FPGA to configure transceiver registers and manage the startup
calibration sequence deterministically. Our findings indicate that Knypaegje
effectively resolves the timing challenges associated with the FELIX cards,
ensuring reliable synchronization for precise time measurements in ATLAS
subdetectors. This work also highlights the importance of adapting
configuration methodologies to maintain system robustness amidst technological
upgrades. In conclusion, Knypaegje not only addresses current FPGA-related
timing issues but also provides a scalable solution for future advancements
within the FELIX architecture.
| Position | TBC |
|---|---|
| Affiliation | TBC |
| Country | TBC |