2–6 Feb 2026
TIFR, Mumbai
Asia/Kolkata timezone

R&D and qualification system development for for ALICE ITS3 MOSAIX sesnsor ASIC

5 Feb 2026, 17:30
15m
TIFR, Mumbai

TIFR, Mumbai

Tata Institute of Fundamental Research, Homi Bhabha Road, Navy Nagar, Colaba, Mumbai 400005, India
Oral Solid state detectors Parallel Session-II

Speaker

AGLIETTA, Luca (Universita e INFN Torino (IT))

Description

In view of LHC Run4 the ALICE experiment will upgrade the innermost three layers of its Inner Tracking System with an innovative vertex detector based on wafer-scale bent Monolithic Active Pixel Sensors. Each layer is realized with only two 50µm thick sensors which are bent to form a cylinder and held in place with carbon foam supports.
The application of air cooling and the integration of all control, data, and power distribution lines directly into the ASIC leave only the silicon sensor and carbon foam in the detector acceptance, resulting in a material budget of 0.09% $X_\mathrm{0}$ per layer.
The design and validation of the first wafer-scale silicon detector for High Energy Physics requires an extensive R&D program, which is now culminating in a full-size and full functionality prototype of ITS3's sensors: the MOnolithic Stitched Active piXel (MOSAIX).
MOSAIX is a stitched sensor of 19 × 266 $\mathrm{mm}^2$. It consist of several components, corresponding to expositions of different portions of the same photolithographic mask connected together. A left end cap contains the readout controller, high speed transmitters and powering pins, 12 identical Repeated Sensor Units host 12 independently powered and controlled pixel matrices each, and a right end cap encloses a further set of powering pins.
The high level of integration poses new verification and qualification challenges, such as validating long-distance signal integrity across stitched interconnects and synchronizing hundreds of pixel matrices, and qualifying high-speed data transmission at wafer level.
A modular test system has been developed for this purpose. It is centered around an FPGA processor card and thanks to a series of adapter boards supports several testing procedures and scenarios, including probing the full chip on wafer, testing individual wire-bonded segments mounted on a large carrier PCB, and qualifying full-scale layers with the same mechanical and electrical configuration as the final ITS3.
This contribution will focus on the design and qualification of MOSAIX, highlighting its requirements, the main R&D results from previous prototypes that drove its design and the development of the test system.

Position PHD Student
Affiliation University of Turin (IT), INFN, CERN
Country Italy

Author

AGLIETTA, Luca (Universita e INFN Torino (IT))

Presentation materials