Speakers
Description
The existing MALTA design is employing low capacitance of the collection electrode together with full depletion of the sensitive volume and is fabricated in Tower 180 nm technology. Currently, further development of the MALTA chip is shifting towards substantially better timing performance (timing resolution <500 picoseconds) as well as improved integration capabilities of the sensor in larger (>2×2 cm2) matrices while maintaining the radiation hardness at the 2×1015 neq/cm2 NIEL achieved with the MALTA2 chip. The underlying objective is the improvement of radiation resilience which indicates the need for a deep submicron CMOS processes. For the MALTA chip technology scaling will dictate a move to the TPSCo 65 nm CMOS process.
In this presentation, we will provide a conceptual design overview that will allow the porting of the current MALTA design to the 65 nm technology node. By systematically combining advanced CMOS circuit, architecture, and process level radiation hardening techniques with optimized circuit design methodologies, we can significantly enhance the analog and mixed-signal performance of event-based silicon pixel sensors without affecting its radiation tolerance.
A first focus area will be the Analog-Front-End where we will exploit the increased capabilities provided by the 65 nm technology node to: improve signal-to-noise ratio thus enhancing sensitivity to particle signals while enabling lower operation voltage; offer increased robustness of the sensor against the degrading effects of radiation exposure; and implement a calibration and functional monitoring strategy. A second focus area will be on the optimization of the digital periphery for higher data throughput, improved integration capabilities, and radiation resilience. To push towards sub-nanosecond timing resolution, we envision the implementation of a simple memory synchronization scheme in an otherwise asynchronous, event-based operation mode. To mitigate risk and overcome potential design bottlenecks, we will follow an incremental approach where the most challenging design aspects will first be implemented in smaller, standalone test chips still in the 65 nm technology node.
We will present in some detail the above ideas while justifying the move to the 65nm technology node. Where possible, experience gained from previous applications will be included. To ensure robust performance, we will outline a comprehensive verification and testing strategy to be employed while acknowledging potential challenges.
| Type of presentation (in-person/online) | in-person presentation |
|---|---|
| Type of presentation (I. scientific results or II. project proposal) | I. Presentation on scientific results |
