Speaker
Description
With the development of high-luminosity colliders, need for 4D particle tracking has arisen. For this to be possible, tracking detectors have a requirement not only for high granularity, but also to have timing resolution of sub 60 ps .
To achieve this, the MiniCactusV2 chip has been designed to study the timing capabilities of non-amplified High Voltage-CMOS sensors, developed in the LFoundry 150 nm process (LF15A). The chip consists of pixels ranging in sizes from 1 mm x 1 mm to 0.5 mm x 0.5 mm. Data from two test beam periods in July 2025 and October 2025 show timing performance of 50 ps can be observed.
Although this achieves the time resolution requirement for 4D particle tracking, the pixel size limits the sensors spatial resolution. In this work, we present the performance of the Cactus Gain Layer (Cactus-GL) chip, a monolithic LGAD (Low-Gain Avalanche Diode) developed in the LFoundry 150 nm process. This device incorporates a novel buried gain layer within a traditional HV-CMOS sensor. The gain layer is implanted deep inside the silicon substrate, removing the need for segmentation and allowing the high fill factor characteristic of HV-CMOS technologies to be preserved. As a result, the goal of this study is to achieve sub-60 ps timing resolution while retaining high spatial resolution , making monolithic LGADs strong candidates for future high-granularity timing detectors.
The Cactus-GL contains six structures: one reference structure without gain, and five variants with differing inter-diode isolation designs. The chip has been fabricated with two gain-layer concentrations on both high-resistivity silicon wafers and epitaxial wafers. Initial results show breakdown voltages up to 260 V for devices on high-resistivity wafers, and up to 140 V for those on epitaxial wafers. Gain has been observed using Strontium-90 beta sources and IR laser measurements. The high-resistivity, high-gain-layer-concentration wafer exhibits the highest gain, enabled by its ability to sustain higher operating voltages.
We will also present measurements of inter-diode channel currents to demonstrate that segmentation of the gain layer is not required to suppress pixel-to-pixel crosstalk. Finally, we discuss planned future work, including a proton-irradiation campaign and the design of the next Cactus-GL iteration . Here, Technology Computer Aided Design (TCAD) simulations have been carried out to first understand the current iterations behaviour. Once this had been characterised within the simulations, further simulations had been carried out to optimise the chip design, with a focus on optimising breakdown voltage and sensor gain.