Speaker
Description
The bPOL12V_FX1 is a radiation-tolerant buck Point-of-Load DC/DC step-down converter manufactured in a commercial 350 nm high-voltage CMOS process and intended for powering HL-LHC front-end electronics. It was developed to supersede the bPOL12V_V6, which exhibited output voltage regulation failures under specific Total Ionizing Dose (TID), bias, and thermal conditions. Implemented in a different technology, bPOL12V_FX1 addresses the vulnerabilities identified in its predecessor. This work presents the complete development flow, covering technology characterization, circuit-level modifications, and experimental validation for High Energy Physics (HEP) environments.
Summary (500 words)
The bPOL12V_FX1 is a radiation-tolerant Buck Point-of-Load DC/DC converter implemented in a 350 nm high-voltage CMOS technology, providing a regulated output of (0.6 V - 3.5 V) from a 12 V input bus. It targets a TID of 80 Mrad, a displacement damage fluence of 5e15 neq/cm^2, and operating temperatures between −40 °C and 80 °C. The converter was conceived to replace the failing bPOL12V_V6 for applications where the risk of irreversible impact on the detector system is significant.
In July 2025, a critical failure mode was observed in the bPOL12V_V6 after a Co-60 irradiation campaign performed by the ATLAS ITK collaboration. The converter lost regulation capability, producing output voltages beyond safe limits and causing irreversible damage to downstream ASICs. This effect, referred to as ”sudden failure”, occurs only for TID levels exceeding 3 Mrad, while keeping the device biased but disabled. The degradation is significantly accelerated at cryogenic temperatures and with increasing TID. The underlying mechanism was identified as a Hot Carrier Injection-assisted post-irradiation recovery of a PMOS transistor in the level shifter, necessitating a revision of the circuit architecture. A dedicated paper illustrates in detail the
failure mechanism and possible mitigation techniques, while this work focuses on the design of the replacement DC/DC ASIC.
Due to the unavailability of the original manufacturing process, the design was migrated to a new 350 nm CMOS technology, characterized for radiation in December 2025, using test-chips produced in 2023. X-ray irradiation campaigns allowed to assess transistor degradation up to 80 Mrad, while Single Event Effects and Displacement Damage response were evaluated at HEARTS and IRRAD facilities, respectively. Simulated ID(Vg) characteristics were fitted to post-irradiation measurements, enabling accurate modeling of TID-induced effects, such as threshold voltage shifts and mobility degradation.
The selected technology provides only 9 V-rated p-type LDMOS, whereas the previous technology provided 25 V-rated devices. Consequently, significant modifications were required in the high-voltage bandgap, linear regulators, and Over Current Protection (OCP) circuits to ensure safe operation of 9 V p-LDMOS, while maintaining a 12 V supply rating.
The extensive testing campaign on bPOL12V_V6 revealed some additional issues, including cross-conduction during the soft-start phase, premature turn-on when the enable pin is driven through a divider from the input voltage, limitation of the maximum achievable Ton, and output voltage rebound during power-down. All root causes were identified and appropriate countermeasures were adopted in the redesign. The ASIC was taped out in March 2026, following a four-month development effort. Functional and radiation qualification tests are scheduled to begin upon prototype delivery in June, and results will be presented at the workshop.
Overall, bPOL12V_FX1 represents a complete technological migration of the bPOL12V_V6, addressing its limitations. The complete development cycle will be presented, including process characterization, a detailed discussion of the implemented design solutions, and final hardware validation for HEP applications.