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Carmelo Scarcella (CERN)28/09/2026, 15:00
High-capacity optical links are required for the readout of next-generation CERN detectors. These systems must satisfy stringent constraints on radiation tolerance, material budget, and power consumption. Silicon Photonics has emerged as the new industry platform for short-reach optical interconnects, meeting these requirements and offering high levels of integration. In this work, we...
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Dr O. Can Akgun (Nikhef National institute for subatomic physics (NL))28/09/2026, 15:00
SENSEIS is a collaborative R&D project developing a MEMS inertial sensor and dedicated readout ASIC for low-frequency seismic sensing, targeting Newtonian-noise monitoring in future gravitational-wave detectors [1]. The system targets 4 ng/√Hz total noise over 1–50 Hz, with 140 dB dynamic range and 0.1 g clipping. The first fully operational readout ASIC, fabricated in XFAB 0.35 µm HV CMOS,...
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Daniel Johnson (University of Birmingham (GB))28/09/2026, 15:20
Modern particle physics detectors present a major readout challenge, both because of the irradiation to be survived by on-detector transmitters and the data volumes that they must accommodate as particle fluxes increase and spatial/timing precision of recorded hits improves. Silicon photonics provides an answer, with custom modulators on-detector but potential for off-the-shelf components...
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Stephen Greenberg28/09/2026, 15:20
The high multiplicity of neutrino events in the DUNE Liquid Argon Near Detector (ND-LAr) requires a high-fidelity 3D-imaging technology capable of handling complex topologies. LArPix is a pixelated charge readout system for Liquid Argon Time Projection Chambers (LArTPCs) based on a cryogenic-compatible ASIC, providing a fully-integrated analog-to-digital signal pathway within the LAr. A...
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Adriano Lai (Universita e INFN, Cagliari (IT))28/09/2026, 15:40
The IGNITE project develops technical solutions for the next generation of trackers at colliders. The final ASIC, the IgnitER, is being designed to have pitch of 45 µm and time resolution on the full chain (sensor to TDC) below 50 ps.
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We present measurements aimed at characterizing the Ignite64, a prototype featuring a matrix of 64x64 pixels and a pitch of 55 µm. Tests are made both with and... -
Audrey Goujon28/09/2026, 15:40
The High Luminosity Large Hadron Collider (HL-LHC) project drives an upgrade of the Radio Frequency (RF) distribution to meet tighter phase noise and phase stability requirements. The Timing, Trigger and Control (TTC) backbone, obsolete and temperature-sensitive, can therefore no longer meet these requirements. The WR2RF module, developed as an end-node of the White Rabbit (WR) network,...
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Filip Pazdic (University of Birmingham (GB))28/09/2026, 16:30
The Central Trigger and Timing architecture for the ALICE3 experiment in Run 5 is presented. Extending the continuous readout paradigm established in ALICE Run 3 and Run 4, the system provides global timing distribution, synchronization, and control without hardware physics triggers. A common back-end platform is considered for the Central Trigger Processor (CTP), Local Trigger Units (LTUs),...
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Thomas Charles Gardiner (Science and Technology Facilities Council STFC (GB))28/09/2026, 16:30
RAL’s ASIC Design Group continues its programme of radiation-hardened 28nm CMOS IP development for future particle-physics experiments, with FURNIX as the latest in a line of test ASICs. FURNIX builds upon the success of the PURNIX and YELNIX ASICs currently under evaluation for radiation-hardness up to 1GRAD at Oxford University, and features a range of sophisticated IP: An Aurora based...
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Pedro Pablo DUMAS ZIEHLMANN (OMEGA - Ecole Polytechnique - CNRS/IN2P3)28/09/2026, 16:50
The CALOROC1B ASIC is a 36-channels ASIC designed to read out large SiPMs (up to 10 nF) for the ePIC calorimeter at EIC using a streaming readout. This work presents the measurement results of the chips received in April 2026. These measurements confirm the linearity and reliability of the gain-switching mechanism, which enables the ASIC to achieve a large dynamic range (from 150 fC up to 1.5...
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Kazuma Maki (ICEPP, The University of Tokyo)28/09/2026, 16:50
We present a clock phase-alignment system for the Phase-2 LHC-ATLAS TGC system, in which all 1,434 front-end electronics modules receive clocks via 1,434 individual fibers. Precise alignment well below 1 ns is required to ensure optimal BC identification with minimal gate width. To address fiber-length–induced clock skew, we developed a dedicated timing calibration system using custom...
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Gianni Mazza (Universita e INFN Torino (IT))28/09/2026, 17:10
The ToRA ASIC is the first prototype for the readout of the MicroMega detectors for the AMBER experiment upgrade.
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Its 64 channels provides 4 programmable gain values and shaping times. It measures the arrival time and the time over threshold of the shaped signal. Moreover, it can also measure the peak time, store the peak value and convert it to digital via a simple single-ramp ADC. The time... -
Raghunandan Shukla (Imperial College (GB))28/09/2026, 17:10
A common challenge in beam tests is that particles do not arrive synchronously to the detector reference clock. Thus, the time of arrival needs to be measured with an external detector. For beam tests of the CMS High Granularity Calorimeter (HGCAL), we used the electrical receivers of CERN’s low-power gigabit transceiver (lpGBT) ASIC to directly digitize a trigger pulse. The signal is sampled...
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Edoardo Orzes29/09/2026, 09:00
New detectors for High Energy Physics are being developed to withstand the high-luminosity upgrade of the LHC. This upgrade increases the requirements for phase stability of the timing distribution systems (<10ps RMS). Commercial transceivers do not meet these stringent requirements, although ad-hoc solutions have been implemented to measure phase drifts and compensate, these are FPGA-specific...
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Marco Andorno (CERN)29/09/2026, 09:00
With increasing digital processing complexity and development costs, the next generation of front-end detector ASICs will greatly benefit from programmable embedded architectures. This work introduces ROSA, an embedded microcontroller on the Picopix chip, for the LS4 upgrade of the LHCb VELO detector. ROSA acts as an on-chip master on the slow control configuration bus of Picopix and can be...
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Aimie Laffitte (OMEGA (FR))29/09/2026, 09:20
CALOROC1C is a 36-channel front-end ASIC designed for Liquid Argon calorimeters in future high-energy physics experiments, with compatibility for Silicon detectors. Derived from the HGCROC architecture, it extends operation to cryogenic environments (77 K) and large detector capacitances. Each channel combines a low-noise front-end with dual-path digitisation, achieving a 10 pC dynamic range...
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Daniel Estrada (Universidad de Oviedo (ES))29/09/2026, 09:20
The CMS Level-1 muon trigger must be redesigned for the High-Luminosity LHC to cope with extreme data rates while remaining sensitive to rare signatures such as long-lived particles. We present recent developments in intelligent muon reconstruction and identification at the trigger level. We exploit low-level hit information from the muon system at MHz rates to detect anomalous shower activity...
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Mr David Peninon Herbaut (CERN)29/09/2026, 09:40
Dynamic IR-drop-induced jitter is a critical limitation in modern high-speed ASICs, affecting both precision timing and high-rate data transmission. Switching activity causes transient supply voltage variations that modulate gate delays and translate directly into timing uncertainty. Accurately estimating this effect at the pre-silicon stage remains an open challenge, particularly for complex...
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Mei-Li Holmberg (University of Bristol (GB))29/09/2026, 09:40
The High Luminosity LHC (HL-LHC) will push triggering systems to their limits due to extreme data rates. In response, the CMS experiment is deploying the Level-1 Track Finder: an FPGA-based trigger subsystem designed to perform real-time track reconstruction at 40 MHz. The Track Finder will reconstruct tracks within a strict 4 µs latency using a custom track-finding algorithm. The additional...
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Olivier Bourrion (Centre National de la Recherche Scientifique (FR))29/09/2026, 11:20
For LHC Run 4, ALICE will use stitched Monolithic Active Pixel Sensors (MAPS) to upgrade its Inner Tracking System (ITS3). The detector will require detector service electronics (DSE) to provide and monitor power supplies, forward clock and timing information, enable remote sensor configuration and monitoring, and convert copper 10 Gb/s serial data links to optical links. Installed within 30...
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Artur Apresyan (Fermi National Accelerator Lab. (US))29/09/2026, 11:20
We present the design and performance of the
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FCFD1.1 constant-fraction discriminator ASIC for precision
timing detectors based on AC-LGAD sensors. The chip,
implemented in 65 nm CMOS, achieves ~40 ps time resolution
and 15–20 μm spatial resolution in beam tests, with full
detection efficiency over the sensor surface. The design
integrates on-chip time-walk correction, reducing reliance... -
Ennio Monteil (Paul Scherrer Institute (CH))29/09/2026, 11:40
LIGHT01 (LGAD-based Integrated Granular Hybrid Timing ASIC) is the first prototype of a readout chip family specifically designed for Low Gain Avalanche Diode (LGAD) pixels. Designed in a 28nm CMOS technology, LIGHT01 incorporates a pixel matrix with 64 channels, each comprising a preamplifier, a discriminator and a time-to-digital converter (TDC), targeting a per-channel time resolution of...
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Angelo Loi (Universita e INFN, Cagliari (IT))29/09/2026, 11:40
The development of hybrid silicon pixel sensors for High-Luminosity LHC experiments is entering a critical prototyping phase. The INFN IGNITE project aims to deliver next-generation 4D tracking readout chips (ROCs) featuring an intrinsic time resolution of σ < 50 ps per pixel. Recent milestones include the debut of IGNITE-64 and IGNITE-32 ROCs, supporting 4096 and 1024 channels, respectively....
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Hanbing Liu (Lanzhou University (CN))29/09/2026, 12:00
The LHCb Upgrade II, scheduled for the 2030s at HL-LHC, encounters extreme pileup, placing stringent demands on high-performance tracking. The Upstream Pixel Tracker (UP) is essential for precise reconstruction upstream of the magnet, with strict constraints on low material budget and long-range 1.28 Gb/s high-speed data transmission.
In this presentation I will introduce the UP layout and...
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Gianmario Bergamin (CERN)29/09/2026, 12:00
FastRICH is a 16-channel, radiation-tolerant front-end ASIC for the LHCb RICH detector upgrade at the High-Luminosity LHC. It delivers precise timestamping of single-photon signals at 40 MHz, with timing resolution better than 30 ps RMS. Compatible with different photodetectors, each channel integrates a low-noise analogue front-end, CFD and LED discriminators, and a TDC with 24.4 ps ToA and...
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Michael Wiebusch (GSI Helmholtzzentrum für Schwerionerforschung GmbH)29/09/2026, 13:40
A discrete front-end circuit for fast scintillation detectors is presented, enabling simultaneous timing and energy measurement using leading-edge discriminators and TDCs. Instead of relying on time-over-threshold, which is sensitive to pulse shape distortions, the circuit samples the pulse amplitude near its peak, stores it, and converts it into a pulse width via controlled discharge. This...
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10. A Flexible FPGA-based Emulator for Front-End Electronics of the CMS High-Granularity CalorimeterHendrik Alexander Krause (KIT - Karlsruhe Institute of Technology (DE))29/09/2026, 13:40
The CMS Phase-2 High-Granularity Calorimeter (HGCAL) employs a high-bandwidth front-end with significant variations in topology and data rates. To support the back-end firmware development, an FPGA-based front-end emulator has been implemented on a Serenity-S1 FPGA board. The emulator framework uses lpGBT link emulation along with output buffer emulation of the key front-end ASICs. Additional...
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Nicholas St. John (Brookhaven National Laboratory)29/09/2026, 13:40
We present a fiber-optic link that simultaneously delivers DC power
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and Manchester-coded slow-control data to a multi-junction GaAs
optical power converter (OPC) operating in a cryogenic environment.
Using a single 808 nm multimode fiber, the link supplies up to 160 mW
of regulated electrical power while transmitting data at 10 kb/s,
with the OPC immersed in liquid nitrogen (LN2) at 77... -
175. A White Rabbit-based test system for reference beacons synchronising autonomous radio detectorsEric Teunis De Boone (Universitaet Siegen (DE))29/09/2026, 13:40
Sub-nanosecond time synchronisation is a key requirement for cosmic ray radio detectors. At installations such as the Pierre Auger Observatory, GPS-based timing is complemented by a continuous-wave reference beacon to correct clock drifts. We present a White Rabbit–based test system to evaluate the accuracy and scalability of this synchronisation scheme. The system records beacon signals at...
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Timo Muscheid29/09/2026, 13:40
Cryogenic detector arrays demand scalable, low-noise readout electronics to preserve their superior energy resolution. Frequency-division multiplexing enables large channel counts but leads to high amplifier power and potential signal distortion when using static carrier tones.
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Continuously tracking the resonance frequencies is mitigating this problem, but requires the readout electronics to... -
Daniel Crovo29/09/2026, 13:40
Multiplexed readout of large cryogenic detector arrays is essential for next-generation particle-physics experiments such as direct neutrino-mass measurements and dark-matter searches. In these systems, online triggering is a key component of the readout chain, enabling real-time pulse detection and selective event storage under low latency and resource utilization constraints. We present a...
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Dmitry Eliseev (Rheinisch Westfaelische Tech. Hoch. (DE))29/09/2026, 13:40
The lpGBT is a radiation-tolerant ASIC enabling high-speed optical communication for high-energy physics experiments. To address prototyping challenges in the designs, which include the lpGBT, we present an FMC mezzanine board and the lpGBT Stream IP Core. The mezzanine provides access to eLinks, clocks, GPIOs and configuration interfaces of lpGBT, allowing prototyping without a need for a...
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Juan José Silva García (GRAF (Group of Radio Frequency) - University of Barcelona)29/09/2026, 13:40
This work optimizes the readout of large-area silicon photomultipliers for time-of-arrival measurements, evaluated in terms of jitter. Unlike conventional direct sensor-to-readout connections, it provides an accurate theoretical characterization of both the sensor and the front-end readout circuit, validated through laboratory measurements, and derives a matching condition to enhance...
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Nikitas Loukas (University of Notre Dame (US)), Piyush Kumar (University of Notre Dame (US)), Stephen Goadhouse (University of Virginia (US))29/09/2026, 13:40
This work presents the firmware architecture and implementation of the Barrel Calorimeter Processor (BCP) for the Phase-2 CMS ECAL Barrel as well as the ECAL refurbishment. The presentation focuses on a single Front-End Driver (FED), addressing resource allocation and key implementation challenges. System performance is validated through a slice test with five Very Front-End (VFE) boards and...
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James Storey (CERN)29/09/2026, 13:40
Timepix3 hybrid pixel detectors installed inside the CERN SPS beam pipe for a Beam Gas Ionisation profile monitor showed intermittent communication loss, resets and pixel-data corruption with intense multi-bunch beams. Initial investigations considered both radiation-induced single-event effects and electromagnetic interference; dedicated tests indicated an EMI origin. EMC laboratory studies...
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Vladimir Sidorenko (Karlsruher Institut für Technologie)29/09/2026, 13:40
Accurate clock and time distribution is a key requirement for the free-streaming data acquisition of the CBM experiment, where timestamped data are reconstructed online at interaction rates of up to 10 MHz. The Timing and Fast Control system distributes the global clock and time to about 200 readout FPGA boards over a hierarchical network of latency-deterministic optical links. A previous...
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Jasmin Barbara Lebert (Goethe University Frankfurt (DE))29/09/2026, 13:40
The ALICE 3 detector will operate at collision rates of 24 MHz (pp) and 300 kHz (Pb–Pb). The resulting hit occupancies demand higher frequencies in the on-chip digital readout of the pixel sensors. To minimize power consumption, the lowest frequency sustaining loss-free data transmission must be determined.
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This work presents a SystemC simulation of the readout architecture to be integrated... -
Mehmet Alp Sarkisla (Bogazici University (TR))29/09/2026, 13:40
This work presents a versatile and robust platform board based on the Zynq SoC architecture. The platform is highly adaptable for a broad range of applications, offering features such as differential clock inputs and outputs with jitter-cleaning functionality, QWIIC expansion, and expandable general-purpose QSH and RJ45 connections. The design and implementation are described in detail,...
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Mr Guillermo Loustau De Linares29/09/2026, 13:40
The ATLAS High-Luminosity TDAQ upgrade seeks to increase the trigger rate from 100 kHz to 1 MHz and provides additional latency for processing. New electronics for the Monitored Drift Tube chambers (MDTs) make it possible to include this precision muon data in the first level trigger. We designed and implemented an ATCA blade including a Service Module based on the APOLLO platform, together...
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Dr Marc Schneider (KIT - Karlsruhe Institute of Technology)29/09/2026, 13:40
Silicon photonic ring modulators are key components for future silicon photonic transmitter systems in particle detectors. It has been shown that standard designs can retain acceptable performance up to a total ionizing dose of approx. 3 MGy, and up to more than 7 MGy when employing annealing techniques. We present a modified design which is expected to increase radiation tolerance...
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Felix Sebastian Nitz (Bergische Universitaet Wuppertal (DE))29/09/2026, 13:40
The Monitoring of Pixel System (MOPS) chip is an ASIC developed to monitor the ATLAS Inner Tracker Pixel modules. Within the Detector Control System (DCS), the MOPS-Hub aggregates data from multiple MOPS chips. However, further integration through the designated DCS interface remains too complex for deployment at integration sites. To address this, a simplified...
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David Bartunek (University of West Bohemia (CZ))29/09/2026, 13:40
This work presents the development of a picoTDC-based NIM module for the ARP project at CERN, designed for precision timing in the AFP (ATLAS Forward Proton) Cherenkov detector Roman Pot system. The module integrates a PolarFire FPGA with the picoTDC ASIC developed at CERN, forming a compact and scalable readout unit. It enables high-resolution time-over-threshold measurements and reliable...
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Dr Philip John Garsed (University of Cambridge (GB))29/09/2026, 13:40
We describe the development of two lpGBT/VTRX+-based front-end readout and control modules - part of the FastRICH-based precision timing readout chain being implemented in the LHCb RICH detector in LS3. As well as increasing bandwidth by 4x in a smaller footprint compared to existing modules, we will show how the design is future-proofed for use in the Upgrade II.
The electro-mechanical...
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Paolo Musico (INFN e Universita Genova (IT))29/09/2026, 13:40
We report the studies for the design of a cryogenic SiPM based camera.
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It is composed by a SiPM matrix handled by a newly developed ASIC: the DENEB.
This chip measure timing and energy information and transmit data in a fast and configurable way.
The system will be immersed in liquid Argon under a moderate magnetic field: the challenges are to make the system working in this particular... -
Prof. Michele Caselle (INFN Bari and University of Foggia)29/09/2026, 13:40
2.5D chiplet architectures and 3D wafer‑to‑wafer integration are rapidly becoming indispensable technologies for next‑generation detector development, but access to these advanced processes is still limited and costly for small‑volume R&D. DRD7.6b addresses this barrier by developing in‑house TSV, RDL, interposer, and 3D ASIC‑integration capabilities while reinforcing collaboration with...
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Benoit Rio (European XFEL)29/09/2026, 13:40
The PIXIE (Plasma Interface for XFEL Atmospheric-Pressure Experiments) R&D project at European XFEL investigates a confined high-current thermal arc as an alternative to conventional solid vacuum-to-air interfaces. The plasma behaves as a nonlinear dynamic load, requiring a short DC pulse up to 1.5 kV for breakdown, transiting to a stable 86 V, 20 A arc and allowing continuous power increase...
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Dr Richard Bates (University of Glasgow (GB))29/09/2026, 13:40
Across a range of materials, SnAg1.8 solder on Cu pillars and indium are widely used in flip-chip bonding for the hybridization of sensor chips to read-out electronics.
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Flip-chip bonding is performed with a range of process to accommodate device specifications and features, for example uneven or curved chips.
Testing a variety of bond parameters such as bond force and developing strategies... -
Zulal Kiraz (CNRS - IJCLab)29/09/2026, 13:40
We present the front-end readout electronics for the LHCb ECAL Phase-II
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upgrade during LS4. The current ECAL will be replaced by PicoCal, designed to sustain higher pile-up, occupancy, and radiation levels with a five-fold increase in granularity across regions with different technologies. PicoCal targets a timing resolution below \SI{15}{ps} over \SI{50}{MeV} to \SI{5}{GeV}, with channel... -
Qader Dorosti Hasankiadeh (Universitaet Siegen (DE)), Vesselin Dimitrov29/09/2026, 13:40
Autonomous radio detection of extensive air showers requires trigger decisions under non-stationary radio-frequency interference, limited bandwidth, and microsecond-scale latency. We present an FPGA-based hardware validation framework for a resource-efficient AI self-trigger aimed at station-level radio detectors. The system combines deterministic trace replay, controlled signal injection,...
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Dominic Ecker (CERN)29/09/2026, 13:40
The ATLAS Detector Control System (DCS) ensures the safe and reliable operation of the detector by providing a standardized interface to all subsystems and infrastructure. The hardware status is currently assessed against static, vendor-defined thresholds and operational status, enforced in the SCADA back-end. The current system is therefore blind to gradual degradation and correlated hardware...
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Eric Oberla29/09/2026, 13:40
The Radio Neutrino Observatory in Greenland (RNO-G) is a detector array in phased construction near the top of the Greenlandic ice sheet, targeting the measurement of ultra-high energy neutrinos. The RNO-G array is composed of independent stations on a ~1.25 km grid, with each station operating autonomously via renewable energy and wireless communications (LTE, LoRa). We present a new...
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Andrej Seljak (Jozef Stefan Institute (SI))29/09/2026, 13:40
Silicon photomultipliers (SiPMs) are candidate photodetectors for the LHCb RICH upgrade II, where they are required to operate reliably in high radiation environments. Critical parameters such as dark count rate, gain stability, and photon detection efficiency were therefore evaluated as a function of neutron fluence. The results indicate a significant increase of DCR, noise and leakage...
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Nikitas Loukas (University of Notre Dame (US))29/09/2026, 13:40
After the Phase-II upgrade of the CERN Large Hadron Collider, precise pile-up discrimination in the CMS Electromagnetic Barrel Calorimeter requires a highly accurate and repeatable clock distribution system. Achieving picosecond-level phase stability across resets is critical to avoid repeated calibration, but standard Field-Programmable Gate Arrays (FPGAs) lack this capability. The Barrel...
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Federico Morodei (Sapienza Universita e INFN, Roma I (IT))29/09/2026, 13:40
The Data Collector and Transmitter (DCT) is a radiation-tolerant FPGA-based board developed for the readout of ATLAS RPC detectors in view of the High-Luminosity LHC upgrade. This contribution presents the hardware test results obtained with the BI-DCT, the DCT version designed for the new BI RPC chambers. Tests performed at CERN with cosmic-ray muons demonstrate excellent timing and spatial...
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Ferran Ortiz Terol, Ferran Ortiz Terol (IFIC, CSIC-UV)29/09/2026, 13:40
The ATLAS experiment at the Large Hadron Collider (LHC) will undergo a major upgrade for the High-Luminosity LHC (HL-LHC), enabling operation at luminosities up to 5–7 times the nominal design value. To meet these new challenging conditions, the ATLAS Tile Calorimeter will completely replace its readout electronics with a new architecture based on a fully digital trigger system.
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This... -
Pawel Kozlowski29/09/2026, 13:40
The development of high‑speed photonic links for next‑generation detector readout requires precise thermal regulation (±0.5 °C) of the micro‑ring modulators in photonic integrated circuits (PIC). Such stability is needed to maintain resonance alignment and ensure reliable 25 Gbps operation. To evaluate the intended ASIC architecture before fabrication, we built a prototype temperature‑control...
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Konstantinos Alexopoulos (Nat. Cent. for Sci. Res. Demokritos (GR))29/09/2026, 13:40
The innermost barrel layer of the CMS Phase-2 Inner Tracker will be replaced half way through the HL-LHC lifetime due to the extreme radiation levels. Rather than a simple replacement, an improved Layer-1 design has been developed, targeting a factor of two reduction in mass to improve tracking performance. A new long-ladder high-density interconnect (HDI) was designed for powering and reading...
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Jeongeun Lee (Seoul National University (KR))29/09/2026, 13:40
Low-Gain Avalanche Diode (LGAD) sensors for the CMS MTD Endcap Timing Layer must retain charge collection (> 8 fC after irradiation) and timing performance at <50 ps level after fluences up to $2.5×10^{15}n_{\mathrm{eq}}/\mathrm{cm}^{2}$, while operating cold ($-25 ^{\circ}\mathrm{C}$) with sufficient bias-voltage margin. We present radiation-tolerance studies of LGAD sensors proton-irradiated...
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Michail Sapkas (Universita e INFN, Padova (IT))29/09/2026, 13:40
This study proposes a 1D Convolutional Neural Network (CNN) architecture designed for real-time particle hit detection, moving beyond traditional rigid triggering thresholds. By processing continuous data streams, including high-noise environments, our model demonstrates superior sensitivity in low Signal-to-Noise Ratio (SNR) regimes and pile up events. We demonstrate that this approach...
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Nour Sharif29/09/2026, 13:40
Modern low-power SRAM-based FPGAs such as the Efinix Ti60 FPGA, fabricated in 16 nm FinFET technology, are emerging as promising candidates for on-detector processing in high-energy physics. These devices offer compact form factor, low power consumption, and cost-efficient integration. However, their radiation tolerance and susceptibility to single-event upsets (SEUs) remain largely...
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Tim Stellhorn (Universität Münster (DE))29/09/2026, 13:40
The Sensor Pixel Asynchronous Readout CMOS (SPARC) aims to evaluate the feasibility of implementing an asynchronous readout logic in a monolithic pixel matrix. The design of pixel detectors like SPARC is supported by the PixESL framework, which provides the opportunity to implement a digital prototype at a high level of abstraction. This contribution will focus on PixESL simulations of the...
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Xinhai Liao (Shanghai Institute of Microsystem and Information Technology, Chinese Academy of Sciences)29/09/2026, 13:40
SHINE is a hard X-ray free electron laser device with pulse repetition rates up to 1 MHz, requiring high-speed pixel detectors such as STARLIGHT with target frame rates higher than 10 kHz . In order to meet its high data transmission requirements while enabling portable detector testing, this work developed a firmware architecture based on TB5. This design integrates power transmission,...
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Gerardo Vasquez (Millennium Institute for Subatomic Physics at High Energy Frontier (CL))29/09/2026, 13:40
Precise timing at the tens of picoseconds level over large detector areas is a key challenge for experiments such as the SHiP experiment. Conventional double-sided readout of long plastic scintillator bars is limited to ~100 ps resolution due to photon transport effects. We present a novel geometry based on distributed SiPM readout along the bar, improving both timing and position...
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Sabrina Perrella (Sapienza Universita e INFN, Roma I (IT))29/09/2026, 13:40
The upgrade of the muon trigger system of the ATLAS experiment for the HL-LHC introduces new DCT and SL boards to handle increased luminosity and rates. The DCT firmware implements a sub-nanosecond TDC based on oversampling using ISERDES primitives in AMD Xilinx FPGAs. A dedicated test bench was developed to evaluate performance in terms of time resolution, linearity, and behaviour at high...
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Hannes Sakulin (CERN)29/09/2026, 13:40
We present an update on the CMS Phase-2 Global Trigger (GT), the final stage of the new Level-1 trigger that will apply the trigger menu to objects identified by upstream trigger systems. To provide space for up to 1000 cut-based or machine-learning based algorithms, the GT is distributed over thirteen processing boards, each featuring an AMD VU13P FPGA. We report on porting the system to the...
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Nikolaos Trikoupis (CERN)29/09/2026, 13:40
At CERN, the High-Luminosity upgrade of the Large Hadron Collider requires the deployment of approximately 2,000 electronic cards to support 1,800 new cryogenic instrumentation channels, interfacing with an existing base of about 10,000 transducer cards.
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This paper presents the redesign of the instrumentation electronics with respect to the original LHC generation, addressing component... -
Lea Katharina Burmeister (Heidelberg University (DE))29/09/2026, 13:40
While heavy WIMP searches have reached unprecedented sensitivities, light dark matter (LDM) remains largely unexplored. The DELight experiment will probe this regime using superfluid 4He as the target, monitored with MMC-based large-area microcalorimeters (LAMCALs) at mK temperatures, providing excellent energy resolution and eV-scale thresholds.
DELight aims at a deadtime-free DAQ system...
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Jiaguo Zhang (Paul Scherrer Institut)29/09/2026, 13:40
Gotthard-II is a charge-integrating silicon microstrip detector designed for energy-dispersive experiments and X-ray photon beam diagnostics at free-electron lasers (FELs) and synchrotrons. Its scientific applications encompass X-ray absorption and emission spectroscopy, X-ray energy diagnostics, photon arrival-time monitoring, and veto-signal generation for pixel detectors. The Gotthard-II...
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Mr Weiming Qian29/09/2026, 13:40
To achieve instantaneous luminosities 5-7.5 times of the nominal value of the LHC, it poses significant challenges to the Trigger and Data Acquisition systems during HL-LHC upgrade. A baseline architecture was chosen for the ATLAS Phase-II upgrade, relying on a single-level hardware trigger.The Global Trigger performs complex algorithms
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on full-granularity calorimeter data. The Global Trigger... -
Nils Heyer (Uppsala University)29/09/2026, 13:40
This contribution presents the Radio Neutrino Observatory in Greenland (RNO-G), designed to measure cosmic neutrinos in the EeV range through an array of radio antennas detecting nano-second-long radio flashes. The RNO-G electronic system is outlined, illustrating how signals are measured from the antennas to the recorded pulses. New instrumentation developments are presented, focusing on...
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Felix Frombach29/09/2026, 13:40
The CBM experiment at FAIR will operate a trigger-less free-streaming DAQ at up to 10 MHz collision rate, generating ~1 TB/s of raw data.
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The Timing and Fast-Control (TFC) system provides deterministic timing and will be extended to aggregate readout congestion signals to generate throttle decisions, preventing overflow-induced data loss.
We present a modular UVM simulation of the Silicon... -
Chihiro Yamada (The University of Osaka)29/09/2026, 13:40
The COMET Phase-I experiment at J-PARC searches for muon-to-electron conversion, a charged-lepton-flavour-violating process. The trigger is generated by a multi-stage FPGA-based system using Cylindrical Drift Chamber (CDC) tracking information and timing information from the Cylindrical Trigger Hodoscope (CTH). The CDC tracking trigger system consists of readout boards, trigger front-end and...
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Christophe Hoarau (LPSC/IN2P3/CNRS)29/09/2026, 15:20
This presentation focuses on the readout electronics for SiPMs and diamond detectors, for real-time monitoring of dose deposition in proton therapy. The principle of particle trajectory reconstruction relies on precise timing measurements, i.e. to achieve millimetre-scale resolution, measurements must be accurate to within 100 ps. To meet this requirement, we have developed 50 channels signal...
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Miaoran Sun29/09/2026, 15:20
We present the monolithic particle sensor prototype Picopix2, implemented in a $180~\mathrm{nm}$ HV-CMOS technology. The sensor is based on a triple-well process with a high-resistivity substrate ($370~\Omega\cdot\mathrm{cm}$). Each pixel integrates a charge-sensitive amplifier with parallel discriminator paths, each equipped with its own TDC, enabling improved timing resolution through...
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Milou Van Rijnbach (CERN)29/09/2026, 15:40
The MALTA2 monolithic pixel sensor in 180 nm CMOS imaging technology has been characterised up to 5x10^15 neq/cm2, achieving >95% hit efficiency at 3x10^15 neq/cm2. This contribution presents the first test beam results of a modified MALTA2 design with increased n-layer doping, targeting efficient operation at the highest fluence. The enhanced doping is expected to improve charge collection...
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Luigi Guiducci (Universita e INFN Bologna (IT))29/09/2026, 15:40
In March 2025 the muon system of the SND@LHC detector was upgraded with Mini Drift Tubes modules. The contribution will describe the new detectors, smaller versions of CMS Drift Tubes, and the electronics for the triggerless time-to-digital conversion and readout, based on the OBDT-theta board for the Phase2-upgrade of CMS Drift Tubes and on a VCU118 board as a backend system. The integration...
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Jelena Lalic (Massachusetts Inst. of Technology (US))29/09/2026, 16:00
We present an end-to-end design flow that connects detector simulation to silicon implementation, enabling realistic characterization of low-power embedded AI inference for noise rejection, clustering, and data compression in MAPS pixel detectors with continuous readout. The flow is technology-agnostic and is exercised here in a 28 nm standard CMOS process to close the simulation-to-silicon...
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Riccardo Paramatti (Sapienza Universita e INFN, Roma I (IT))29/09/2026, 16:00
The CMS Electromagnetic Calorimeter (ECAL) barrel is being upgraded for HL-LHC operation while preserving its existing PbWO₄ crystals and APDs. The readout electronics have been fully redesigned to sustain trigger rates up to 750 kHz, increased latency, higher radiation levels, and improved timing performance. New front-end ASICs provide dual-gain amplification, 12-bit digitization at 160...
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Grzegorz Deptuch (Brookhaven National Laboratory (US))29/09/2026, 17:40
The ePIC Silicon Vertex and Tracking (SVT) detector at the Electron–Ion Collider employs serial powering for most barrel layers and requires congregation of resource delivery, motivating an Application-Specific Integrated Circuit providing multi-power-domain shunt regulation, negative bias generation, slow-control management, and monitoring for MAPS-based sensors. Implemented in a 0.11 µm HV...
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Michael Lupberger (University of Freiburg (DE))29/09/2026, 17:40
Within LS4, the LHCb experiment will undergo its major Phase-IIb upgrade. The spectrometer's downstream SciFi tracker will be replaced by a hybrid detector designed to handle higher occupancies and radiation levels. The central high-occupancy regions will employ Monolithic Active Pixel Sensors, while the outer regions will use Scintillating Fibres read by cryogenically cooled Silicon...
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Michela Greco (Universita e INFN Torino (IT))29/09/2026, 18:00
The INFN SPECTRE (Single Photon Emission Computed Tomography Readout Electronics) project aims to design, assemble, and characterize a complete detection module based on CZT sensors for medical applications. For readout, SPECTRE uses the electronics developed for a high-capacitance gas detector (CGEM@BESIII, IHEP, Beijing): the TIGER (Torino Integrated GEM Electronics for Readout) ASIC for...
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Davide Chiappara (CERN)29/09/2026, 18:00
This contribution presents the development of a system level simulation using PixESL to assess quantitatively the performances of the tracking devices developed within ALMIRA (ALice3 Monolithic Integrated tRacking Asic) project for ALICE upgrade. This fully developed simulation runs in about 30 second per orbit per cm2 and guides the design by estimating key ASIC performance metrics: timing...
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Gianluca Aglieri Rinella (CERN)30/09/2026, 09:00
MOSAIX is a wafer‑scale Monolithic Active Pixel Sensor (MAPS) implemented in a 65 nm CMOS imaging process using stitching, with overall dimensions of 266×19.6 mm². It integrates all the functionalities required for the ALICE ITS3 Upgrade.
This contribution provides a retrospective view of the development and implementation of the MOSAIX chip. It focuses on implementation challenges arising...
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Ignacio Redondo Fernandez (CIEMAT - Centro de Investigaciones Energéticas Medioambientales y Tec. (ES))30/09/2026, 09:00
The BMTL1 system is the trigger and readout backend of the CMS Barrel Muon during HL-LHC. 30 custom design ATCA bmtl1 boards generate station primitives running complex logic on VUP13 FPGAs using the full precision data sent by the upgraded frontend of the muon detector. A second layer of 12 bmtl1 boards aggregates wedges easing the transition to TMT-18 scheme used by next trigger layers. Its...
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Alberto Perro (CERN)30/09/2026, 09:20
A primary challenge in High Energy Physics (HEP) data acquisition is the aggregation of numerous low-speed (10Gb/s) radiation-hard data links into high-speed back-end interfaces. While high-end FPGAs traditionally perform this task, transceiver density and speed in modern devices can limit cost-effective scaling. This study proposes a two-stage architecture that utilizes mid-range FPGAs for...
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Dr Simone Scarfi' (CERN)30/09/2026, 09:20
The MOSAIX is a wafer-scale, full-functionality prototype ASIC for the ALICE Inner Tracking System (ITS3) upgrade, implemented in $65\,nm$ stitching technology.
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It integrates 144 independently powered pixel matrices, eight $10\,Gb/s$ serializers, and on-chip data and power distribution, making full-chip verification highly resource-intensive (over $80\,GB$ of memory and 175.000 tests).... -
Yifan Yang (Universite Libre de Bruxelles (BE))30/09/2026, 09:40
Scalable communication is needed for PEPS,a future gamma-ray array of 10
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km2 with 55 solar-powered detector stations per km² at the Pierre Auger
Observatory. With the legacy access radio unavailable for PEPS, we propose a two-tier architecture: a 2.4 GHz FLRC fixed-slot first-hop layer from stations to a per-cell aggregation node, followed by 5 GHz backhaul to the DAQ. Separating access from... -
Dominik Dobrijevic (CERN)30/09/2026, 09:40
The MOSAIX (MOnolithic Stitched Active pIXel) detector is a wafer-scale silicon sensor for the ALICE ITS3 upgrade. Measuring 26.6 × 1.96 cm$^2$ it operates with air cooling, limiting its power budget. It features a high-speed data hub, accumulating information from the 144 independent pixel matrices. Powering five domains exclusively from the short edges presents constraints: analog IR drop...
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Ola Slettevoll Groettvik (CERN)30/09/2026, 11:20
The ALICE ITS3 upgrade for LHC Run 4 employs a stitched, wafer-scale monolithic active pixel sensor for the first time in high-energy physics. MOSAIX, the final full-scale prototype, integrates 144 independently powered pixel matrices, eight 10 Gb/s transmitters, and on-chip power and data distribution across 27 cm. The qualification system developed prior to sensor delivery proved critical in...
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Alessandro Lapertosa (Universita e INFN, Catania (IT))30/09/2026, 11:20
Silicon pixel modules developed for the Phase2 CMS Inner Tracker were tested at HiRadMat facility, CERN, to evaluate potential damage in case of accidental beam loss at HL-LHC. Four pixel modules equipped with RD53 CROCv2 ASIC were exposed to fast and high intensity pulses of 440 GeV protons from SPS. The intensity of pulses was increased step-by-step: single bunch with increasing intensity up...
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Maximilian Babeluk30/09/2026, 11:40
The ALICE ITS3 upgrade for LHC Run 4 uses stitched wafer-scale MAPS, enabling a material budget of $0.9\%\ X_0$ per layer with bent, $50\,\mu m$ thick modules. The full-scale prototype sensor, MOSAIX, integrates power and data distribution, power-gated sensor tiles, and high-speed transmitters. System integration and performance aspects including power, electrical, optical and signal...
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Patryk Semeniuk (AGH University of Krakow (PL), Goethe University Frankfurt (DE), GSI Helmholtzzentrum für Schwerionenforschung GmbH (DE))30/09/2026, 11:40
The Silicon Tracking System (STS) of the CBM experiment at FAIR requires a compact, high throughput readout architecture capable of operating at interaction rates up to 10 MHz. The STS Readout Board (STS-ROB), based on GBTx ASICs and Versatile Link optical interfaces, implements the data aggregation stage between front-end electronics and the back-end data acquisition system. The final...
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Szymon Bugiel (CERN)30/09/2026, 12:00
For the LS3 ALICE ITS3 upgrade, an ultra-light (0.09\% X0 per layer) vertex detector based on wafer-scale monolithic pixel sensors thinned to 50 $\mu$m is being developed. MOSAIX is the full-scale, full-functionality prototype, integrating power distribution, signal processing, and data transmission on-chip. This contribution presents measurement results of MOSAIX, focusing on pixel matrix...
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Ioannis Mesolongitis (University of West Attica (GR))30/09/2026, 12:00
Abstract —
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A mass-production tester was developed for the RPC DCT boards of the ATLAS Phase-II upgrade, covering both legacy BM/BO and new BI detector variants. The system validates complete board functionality during prototype, pre-production, and forthcoming production phases. It emulates the RPC Sector Logic interface and 288 front-end hit inputs using representative 1 MHz, 12.5 ns pulses.... -
Antonio Ocarino01/10/2026, 09:00
bPOL12V_V6 is the production-grade version of a radiation-tolerant DC-DC buck converter designed in a commercial 350 nm high-voltage CMOS technology for HL-LHC front-end electronics supply, with over 100k units manufactured. In July 2025, a critical failure mode was identified during ATLAS ITk stave/petal testing: upon re-enabling after a post-irradiation time spent biased but disabled, the...
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Hancen Lu01/10/2026, 09:00
ALTIROC-A is the front-end readout ASIC of the ATLAS High-Granularity Timing Detector (HGTD). Its large-scale production requires reliable wafer-level screening before dicing and module assembly. This contribution presents the ALTIROC-A wafer probing campaign, focusing on measured performance, including TDC and jitter characterization, wafer-to-wafer yield spread, and the constraints relevant...
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Theresa Alexandra Goldschmidt (University of Zurich (CH))01/10/2026, 09:20
The High-Luminosity LHC(HL-LHC) will reach instantaneous luminosities
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up to $7.5\times10^{34},cm^{-2}s^{-1}$. The CMS Inner Tracker will be replaced to handle higher data rates, increased radiation, and finer
granularity. The new Inner Tracker(IT) uses hybrid modules based on RD53 65nm CMOS ASICs, bump-bonded to silicon sensors with a pixel size of $25\times100,\mu\text{m}$ and operated in... -
Daniel Hernandez Montesinos (CERN)01/10/2026, 09:20
The bPOL12V is a radiation-tolerant DC-DC converter designed for use in high-energy physics experiments, providing low power to the front-electronics of various HL-LHC subdetectors. In 2024, the bPOL12V_V6 was conceived to be the final version, with over 100k units produced. However, a design issue known as “sudden failure” was identified during the ATLAS ITk tests: devices irradiated to 70...
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Dr Dennis Sperlich (University of Siegen)01/10/2026, 09:40
The ATLAS Phase‑2 silicon‑strip tracker will power its modules with a point‑of‑load DC‑DC converter (bPOL12V) mounted directly on the sensor. Irradiation tests (50 Mrad) revealed a radiation‑induced defect that drastically shortens the safe standby time of the ASIC during cold operation. In power‑down mode the defect appears after only 10–120 min, destroying the chip. Without mitigation,...
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Tiankuan Liu (Brookhaven National Laboratory (US))01/10/2026, 09:40
ALFE2 is a front-end ASIC designed for the ATLAS Liquid Argon Calorimeter (LAr) in the High-Luminosity Large Hadron Collider (HL-LHC) upgrade. It integrates four channels of preamplifiers and shapers, each with two distinct gain outputs that can be read out in parallel to cover a 16-bit dynamic range. Over 80,000 chips have been fabricated in a 130 nm CMOS process. A robotic system performs...
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Cecilia Borca (Universita e INFN Torino (IT))01/10/2026, 11:20
Upgrading the CMS ECAL barrel for the HL-LHC requires replacement of all on-detector electronics, including 12,240 Very-Front-End (VFE) cards employing CATIA and LiTE-DTU ASICs for amplification and digitization of signals from ECAL’s 61,200 lead-tungstate crystals.
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All production VFEs undergo the same qualification procedure: functional testing, environmental stress screening, and... -
Pablo Daniel Antoszczuk (CERN)01/10/2026, 11:20
The low-voltage supply of the High Granularity Calorimeter (HGCAL) Phase-2 upgrade of CMS relies heavily on the bPOL12V ASIC for the front-end electronics of the detector. The recently discovered radiation weakness in bPOL12V poses a significant challenge for HGCAL, as over 62k bPOL12V are needed, exposed to a very heterogeneous radiation field up to 40Mrad. With the detector in production...
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Marta Macaluso01/10/2026, 11:40
The bPOL12V_FX1 is a radiation-tolerant buck Point-of-Load DC/DC step-down converter manufactured in a commercial 350 nm high-voltage CMOS process and intended for powering HL-LHC front-end electronics. It was developed to supersede the bPOL12V_V6, which exhibited output voltage regulation failures under specific Total Ionizing Dose (TID), bias, and thermal conditions. Implemented in a...
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Jie Yi (Central China Normal University CCNU (CN))01/10/2026, 11:40
The Bergen pCT collaboration is building a prototype Digital Tracking Calorimeter for clinical proton-therapy use. Quality assurance of the ALPIDE assemblies is performed with a Production Test Box in a joint LTU Kharkiv and University of Bergen (UiB) workflow. The assembly procedure uses chip cables and two qualification stages at LTU: chip tests after bonding to the chip cable, and repeated...
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Liv Anke Richter (ETH Zurich (CH))01/10/2026, 12:00
The upgrade of the CMS electromagnetic calorimeter barrel for operation at HL-LHC requires a new three-stage low-voltage power-conversion system (LVPCS). We present the characterisation and stability analysis of this cascade LVPCS, performed by combining average small-signal modelling, SPICE simulation, and vector network analyser (Bode100) measurement, employing a custom parallel-injection...
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Dr Dima Maneuski (University of Glasgow (GB))01/10/2026, 12:00
ATLAS Inner Tracker (ITk) pixel module production is underway and scheduled for completion in Q2 2027. The detector will cover about 13 m² of active area and include roughly 9,400 quad and triplet modules. Ahead of production, nearly 93,000 readout chips were fabricated and individually qualified to meet stringent ITk requirements. This contribution summarises experience gained in developing...
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Stefano Caregari (Massachusetts Inst. of Technology (US))01/10/2026, 15:20
Next-generation pixel detectors for high-energy physics rely on high-speed links exceeding 10 Gbps, making efficient and reliable production quality control (QC) a critical challenge. This work introduces a high-speed wafer-level testing approach based on vertical probe card technology, enabling multi-Gbps validation directly at wafer-level. Test results obtained on MOSAIX, a MAPS developed...
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Emanuele Romano (Pavia University and INFN (IT))01/10/2026, 15:20
This work presents the development of an ultra-low-latency asynchronous trigger board for testing calorimeter prototypes at CERN SPS. Standard NIM or FPGA-based solutions introduce excessive latency (60-70 ns), incompatible with the requirement that the trigger precede QDC signals by at least 15 ns. To meet this requirement, a custom board based on discrete NECL components was designed. The...
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Dr Nicolo Vladi Biesuz (Universita e INFN, Ferrara (IT))01/10/2026, 15:40
The INFN Data Acquisition system (IDAQ) is designed for data-driven readout of the Timepix4 ASIC, supporting simultaneous time-of-arrival and time-over-threshold measurements with nanosecond precision. The system architecture combines dedicated hardware for high-speed serial data transmission, FPGA-based data processing, and a Trigger Logic Unit for synchronization and timing distribution. It...
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Luise Poley (Simon Fraser University (CA))01/10/2026, 15:40
The replacement of the ATLAS Inner Detector with the new ATLAS Inner Tracker for the LHC High-Luminosity Upgrade will require the assembly of 17,000 silicon strip modules. In preparation for production, scheduled to take place in 30 institutes worldwide over 3.5 years, a pre-production programme was conducted, assembling 5% of the full production quantity. During pre-production, the discovery...
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Angelos Zografos (CERN)01/10/2026, 16:00
This contribution reports two unexpected findings from ATLAS ITk Outer Barrel production and testing with consequences for QC and detector operation. A module-cell isolation defect, due to weaknesses in the original loaded local support (LLS) design, showed an unusual electrical signature that was studied with dedicated measurements to define automatic detection criteria. In addition, a...
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Sandro Geminiani (Universita e INFN, Bologna (IT))01/10/2026, 16:00
The RDO (ReaDOut card) is the main board developed for the readout system of the dual-radiator RICH (dRICH) detector, designed for the ePIC experiment at the future Electron-Ion Collider (EIC). The dRICH DAQ system is organized in 1248 Photon Detection Units (PDU) each integrating 4 ALCOR64 ASICs connected to the RDO FPGA-based card, for reading up to 256 pixel SiPMs. This work discusses the...
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Miroslaw Firlej (AGH University of Krakow (PL))01/10/2026, 17:40
The design and measurement results of a prototype high-speed serialiser and transmitter fabricated in CMOS 65 nm technology are presented. The serialiser, with an architecture based on a multi-phase PLL clock generator, is designed to serialise digital data from multi-channel analogue-to-digital converters or other digital inputs. It outputs a serial data stream of up to 10 Gb/s, with 8b/10b...
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Oi Ying Wong (Nikhef National institute for subatomic physics (NL))01/10/2026, 17:40
A high-resolution, monotonic DAC is essential for precise global threshold setting in the Picopix pixel detector chip, enabling accurate S-curve extraction and reliable control of effective per-pixel thresholds after trimming. Conventional R-string or current-steering architectures scale poorly in area or suffer from non-monotonicity due to device mismatch. This work presents a 12-bit ∑∆DAC in...
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Xiongbo Yan (Institute of High Energy Physics)01/10/2026, 17:40
Addressing the need for higher data rates in high-energy physics readout links, this work introduces a four-level pulse-amplitude-modulation (PAM4) transmitter with a 2-tap feed-forward equalizer (FFE), implemented in a 55-nm CMOS technology. An initial version employs a PRBS pattern generator (2^7-1) instead of a silicon-proven 16:1 serializer to save area and validate the PAM4...
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Mr Longkai Li (Central China Normal University)01/10/2026, 17:40
We present designs and test results of a 25 Gbps VCSEL driving ASIC fabricated in a 55 nm CMOS technology for detector front-end readout. This ASIC proposed a new output driver design using the double-feedforward capacitor compensation, combined with the T-coil technique (customized on-chip inductor) and the adjustable FFE pre-emphasis structure to achieve 25 Gbps bandwidth in 55 nm...
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Xiaoting Li (IHEP)01/10/2026, 17:40
High‑resolution time‑to‑digital converters (TDCs) are essential for time-of-flight positron emission tomography and high-energy physics experiments. We present a TDC core (xpdTDC) implemented in a 55-nm CMOS process. The architecture employs a ring‑oscillator‑based delay line coupled with a passive timing interpolation circuit, using a circular interpolation strategy to achieve a 5.2-ps...
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Alexander Friedrich Elsenhans (KIT - Karlsruhe Institute of Technology (DE))01/10/2026, 17:40
A compact single-shot time-to-digital converter (TDC) implemented in 16 nm FinFET technology is presented for ultra-fine timing in future pixel detector readout systems and 3D-integrated architectures. The design employs a gated ring oscillator combined with a high-speed cycle counter and is implemented exclusively using standard cells. Measurements show an effective LSB size of approximately...
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Prof. Di Guo (Central China Normal University)01/10/2026, 17:40
We present the designs and test results of a 2.56 Gbps Clock and Data Recovery ASIC fabricated in a 55 nm CMOS technology. The ASIC mainly consists of a bang-bang phase detector, a charge pump circuit, a low-pass filter and a LC-VCO circuit. The two-step capacitor tuning structure and a novel capacitor array unit are adopted in the LC-VCO circuit. The test results show that the ASIC outputs the...
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Datao Gong (Fermi National Accelerator Lab. (US))01/10/2026, 17:40
A low-power, high-precision TDC for ePIC timing detector readout is presented in a 65 nm CMOS process. The design features a self-calibrated architecture, providing a compact implementation and PVT robustness suitable for pixel readout. Time resolution is enhanced using a multi-timestamp reconstruction technique with a programmable range of 2 to 65 timestamps. Using triangular-weighted...
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Joaquim Pinol Bel (IFAE)01/10/2026, 17:40
This contribution presents a high-resolution TDC architecture designed for high-density timing applications. While initially developed for the CACTUS R&D timing detector, the design offers a scalable solution for any system requiring sub-10 ps precision with minimal area overhead. The TDC is based on a digital un-tuned oscillator built with 64 inverters, providing a time resolution of 8 ps....
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Mr 铮 王 (中国科学院高能物理研究所)01/10/2026, 17:40
This report presents LATRICi, a novel pulse-interleaved time-to-digital converter (TDC) implemented in a 55nm CMOS process. As an evolution of the initial version based on an event-driven ring oscillator architecture, the proposed design enhances resolution and reduces mismatch through optimized delay cells and a novel latch-pulse-interleaved circuit, achieving an average unit delay of 22.5 ps...
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wangna@ihep.ac.cn wangna01/10/2026, 17:40
The Polarimetry Focusing Array (PFA) of the planned eXTP mission employs three identical X-ray imaging telescopes for polarimetry in the 2–8 keV band. Each detector integrates a radiation sensor with a dedicated ASIC for precise charge readout. We present a self-triggered ASIC with reconfigurable event-driven windows and a two-stage analog readout architecture. A 70×60 pixel prototype (50 μm...
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Mark Pesaresi (Imperial College (GB))01/10/2026, 17:40
A burn-in campaign of the Phase-2 CMS Outer Tracker backend electronics is performed on pre-production Serenity and Apollo boards prior to deployment. The setup consists of two fully populated ATCA crates, with all optical links active simultaneously, enabling operation in a realistic and highly interconnected environment. Particular emphasis is placed on validation of optical interfaces...
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Adrien VERPLANCKE01/10/2026, 17:40
EICROC is a readout ASIC for AC-LGAD sensors developed for the future Electron-Ion Collider at Brookhaven. It targets precise timing and accurate vertex reconstruction.
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Designed as a System-on-Chip, it processes signals through two parallel paths: a fast path for Time-of-Arrival and a slow path for charge measurement, both with on-chip digitization.
The first prototype, EICROC0, and its... -
Matteo Magherini (CERN)01/10/2026, 17:40
The CMS Phase-2 Outer Tracker is progressing toward large-scale system validation ahead of LS3 installation. Multi-module mechanical structures— ladders, rings, planks, and dees— assembled and characterized at integration centers, are brought together into higher-level structures and tested at the Tracker Integration Facility at CERN with final services and complete readout architecture. Noise...
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Dr Ke WANG (Institute of High Energy Physics，Chinese Academy of Sciences)01/10/2026, 17:40
This paper presents a low-noise readout application-specific integrated circuit（ASIC） optimized for three-dimensional position-sensitive cadmium–zinc–telluride (CZT) detectors. Specialized cathode channels are incorporated to accommodate the large planar cathodes of pixelated detectors. Simulation results indicate an anode noise of 64$\mathrm{\ }$$e^-$+8 $e^-$/pF and a cathode noise of...
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Joel Daricou (CERN)01/10/2026, 17:40
The qualification of radiation-tolerant DC/DC converters for high-energy physics experiments requires reliable, reproducible, and easily deployable test infrastructures across multiple external facilities. Issues identified in late 2025 with the bPOL12 converter highlighted limitations of existing test setups, triggering at CERN the design of a universal test platform, the DC/DC Universal Test...
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Luca Ghislotti (INFN Pavia & University of Bergamo)01/10/2026, 17:40
This contribution presents the design and characterization of an analog channel developed in a 65 nm CMOS process. Designed for the readout of large-area silicon-strip detectors, it integrates a low-noise, wide dynamic range charge-sensitive amplifier (CSA) followed by a filtering stage for signal-to-noise optimization. Dynamic signal compression, achieved via a novel dynamic-threshold MOSFET...
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Dr Huaishen LI (IHEP)01/10/2026, 17:40
Abstract: SIPAC is a 4-channel ASIC prototype for SiPM readout in CEPC's ECAL, HCAL, LumiCal, and Muon detector. The chip integrates preamplifier, shaper, ADC, TDC, and serializer. A DAC calibrates SiPM gain, with each channel featuring a dedicated calibration path for single-photon calibration. The chip has been taped-out, and silicon testing is expected to be completed in August....
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Vladimir Gromov (Nikhef National institute for subatomic physics (NL))01/10/2026, 17:40
A new silicon tracker detector (ITS3) will be installed in the ALICE Inner Tracking System during the LHC Long Shutdown 3 [1]. We have developed a 10.24 Gbps Data Serializer and Wireline Transmitter (GWT-PSI) circuit for the detector readout. A 16-to-1 multiplexer architecture achieves low power consumption and avoids high-frequency (> 640MHz) clock signals in the circuit. A power-supply...
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Gabriele Ciarpi (CERN)01/10/2026, 17:40
This work presents a radiation-tolerant, multi-stage serializer designed in 28 nm CMOS, aggregating 80 streams into a single 25.6 Gb/s channel. The architecture employs a multi-stage (80:16, 16:4, and 4:1) approach featuring a quad-rate output stage and integrated pre-emphasis taps to compensate for channel losses. By applying radiation-hardening techniques only to critical control signals and...
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Dr Yang Zhou (Institute of High Energy Physics, CAS, Beijing, China)01/10/2026, 17:40
Driven by LHCb Upgrade II Upstream Tracker and CEPC Inner Tracker, the COFFEE series of HV-MAPS is developed in a 55 nm process. It targets <5 ns time resolution, ~10 μm spatial resolution, and <200 mW/cm² power consumption at a hit density up to 100 MHz/cm². The small-scale COFFEE3 prototype integrates two independent architectures: NMOS-only in-pixel circuitry, and CMOS in-pixel TDC, to meet...
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Alberto Arcusa Puente (Aragon Institute of Technology Itainnova (ES))01/10/2026, 17:40
This work presents an electromagnetic compatibility (EMC) characterization focused on noise sensitivity in the data acquisition reference system and the Micromegas detector of the BabyIAXO prototype. The dominant noise coupling mechanisms affecting the system baseline are identified and analyzed. We ensure measurements in an EMC-clean environment, by using the ITA anechoic chamber. We propose...
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Flavio Loddo (Universita e INFN, Bari (IT)), Giuseppe De Robertis (Universita e INFN, Bari (IT))01/10/2026, 17:40
In this work the design of FATIC4, a new readout ASIC in CMOS 130 nm for the µ-RWELL-based detectors proposed for LHCb upgrade II muon system, is described. A previous version of the ASIC, FATIC3, was successfully tested in laboratory and during test beam campaigns with µ-RWELL-prototypes. Its main limitation was its dead time of about 1us, not compatible with the expected signal rate of about...
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Joelle Savelberg (Rheinisch Westfaelische Tech. Hoch. (DE))01/10/2026, 17:40
The bPOL48V is a point-of-load DC-DC buck converter developed at CERN and characterised at RWTH Aachen University within the DRD7 program. Targeting future high-energy physics experiments, it reduces cable power losses by converting a 48V input to a 5-24V output using a GaN-based power stage.
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Currently, CMS silicon strip modules use DC-DC converters to convert 12V to 1.25V in a two-step... -
Iain Sedgwick (Science and Technology Facilities Council STFC (GB))01/10/2026, 17:40
In this work we report on the first results from a Shunt LDO (SLDO) for use in the serial powering chain of staves at the Electron Ion Collider (EIC). The device is designed in a 110nm CMOS technology and has been tested for load currents from 40mA to 900mA over an output voltage range of 1.0 to 1.4V. Tests are being carried out at temperatures from -20 to 105 degrees Celsius. First serial...
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Jakub Moron (AGH University of Krakow (PL))01/10/2026, 17:40
The design and results of mass tests and detailed characterisation of the second fabrication run of a SoC readout ASIC, called FLAXE, are presented. The FLAXE has been developed for the ECALpelectromagnetic calorimeter at the LUXE experiment. The ASIC consists of 32 channels, each comprising a programmable gain preamplifier, a fully differential shaper, and a 10-bit SAR ADC working nominally...
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Sara Portero Castillo (Universitat de Barcelona)01/10/2026, 17:40
Timing resolution is of paramount importance in Particle Physics Experiments, and many other time-of-flight systems, such as Positron Emission Tomography (PET) LIDAR or mass spectrometry, since it directly translates to better image quality. This work will study what are the most relevant parameters (noise, bandwidth, parasitics, etc.) of a Front End readout circuit to optimize timing...
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Jesus Pena Rodriguez (Bergische Universität Wuppertal)01/10/2026, 17:40
Analog-to-Digital converters (ADCs) have been widely used to measure signal charge and amplitude due to their precision, measurement range, and linearity. Nevertheless, power consumption, data volume, and bandwidth make them unfeasible for the next generation of high-energy physics experiments. Time-over-Threshold (ToT) circuits offer simplicity, low power consumption, ease of integration, and...
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Jia WANG (Northwestern Polytechnical University)01/10/2026, 17:40
Cadmium Zinc Telluride (CZT) detectors are featured as high energy resolution and room-temperature working. Nevertheless, short lifetime of holes in CZT crystals results in energy spectrum broadening for high-energy particles. To address this issue, precise depth-of-interaction (DOI) is required to correct the energy spectrum.
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This report presents the design of a multi-channel... -
Miquel Ribalda Galvez (University of Barcelona (ES))01/10/2026, 17:40
This work presents the first silicon results of a 12-bit low-power SAR ADC fabricated in 65 nm CMOS for multi-channel detector readout applications. The design targets >40 MS/s operation, sub-mW power consumption, and a compact area (0.036 mm²). It uses a fully differential architecture, a segmented capacitive DAC, a dynamic comparator, and asynchronous control logic to maximise efficiency. A...
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Dr Dirk Wiedner (Technische Universitaet Dortmund (DE))01/10/2026, 17:40
The second upgrade of LHCb is aiming at an instantaneous luminosity of $1.0\times 10^{34}cm^2/s.$ The current downstream tracking system is replaced by an inner pixel tracker and an outer scintillating fibre tracker. The $8\,m^2$ inner pixel detector is based on $4\,cm^2$ sized High Voltage Monolithic Active Pixel Sensors (HVMAPS). Five HVMAPS are mounted on one module. For the efficient...
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Mr Yuanhong Jiao (Northwestern Polytechnical University)01/10/2026, 17:40
This paper presents a system-level modeling methodology for current-steering DACs in front-end readout ASICs using User-Defined Nettypes (UDN). To overcome the limitations of SPICE (low speed) and traditional wreal (lack of loading effects), a VIZ (Voltage-Current-Impedance) structural UDT (User-Defined Type) is implemented with User-Defined Resolution (UDR) based on nodal admittance analysis....
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Laurent Royer (Université Clermont Auvergne (FR))01/10/2026, 17:40
The ATLAS HGTD detector must meet low-noise requirements at the system level to achieve a time resolution of 50 ps per hit during the HL-LHC operations. Consequently, an optimal grounding and shielding strategy is required, which must be evaluated and refined throughout the detector’s development. Measurements on the demonstrator setup revealed excessive common mode conducted noise on power...
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Ahmed Qamesh (Karlsruher Institut für Technologie (KIT))01/10/2026, 17:40
The CMS Phase-2 upgrade introduces a new high-granularity calorimeter (HGCAL). The HGCAL back-end will use about 300 Serenity-S1 FPGA boards using Samtec FireFly electro-optical modules with a link speed of up to 25 Gb/s. Existing production tests only validate the high-speed links via copper loopback cables. We present an Optical Acceptance Test (OAT) framework providing comprehensive link...
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Krzysztof Piotr Swientek (AGH University of Krakow (PL))01/10/2026, 17:40
This contribution outlines the design of the novel PACIFIC++ readout ASIC in CMOS 65 nm for LHCb Mighty-SciFi for LHCb Upgrade II. The architecture incorporates low-noise analogue front-end, amplitude and timing measurements using ADC and TDC embedded in each channel, followed by on-chip data processing and clustering, to meet the stringent speed and power requirements of next-generation...
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Mr Alberto López (ICCUB)01/10/2026, 17:40
This work presents the analog design and performance of the ICECAL65 ASIC, a 4-channel ASIC developed in a 65 nm CMOS technology specifically designed to be included in the Front-End Board (FEB) of the LHCb Upgrade II calorimeter. This ASIC enables the continuous readout of Photomultiplier Tubes (PMTs) with a 12-bit resolution and a power consumption of ~ 50 mW per channel. The ASIC is...
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Llorenç Fanals-i-Batllori01/10/2026, 17:40
This work presents a cryogenic mixed-signal ASIC for noble-liquid time projection chambers (TPCs) targeting next-generation dark matter experiments such as XLZD \cite{xlzd2024}. Fabricated in CMOS TSMC 28-nm technology, the single-channel prototype integrates three parallel low-input-impedance transimpedance amplifiers with gains of 1, 1/40, and 1/400 to accommodate the wide dynamic range...
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Bilal Hasan Qureshi (University of Bergen (NO))01/10/2026, 17:40
The University of Bergen is involved in the design and development of the Electromagnetic Forward Calorimeter (FOCAL-E). This is a major upgrade for LHC Run 4 to the ALICE experiment at CERN. This paper presents the power board design for FOCAL-E pixel layers that provides power to the ALPIDE sensor strings connected to a transition card. The design comprises radiation-hard bPOL48V modules...
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Mr Bendik Husa (University of Bergen (NO))01/10/2026, 17:40
For the planned FoCal-E subdetector in ALICE, the ALPIDE pixel modules are currently being assembled and there is a need to qualify them for use. The pixel modules are tested in three stages: isolated test, assembly test and integration test. To do this, a production test system has been adopted from the Bergen proton CT project along with changes based on experiences gained. In particular,...
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Vlad-Mihai Placinta (Horia Hulubei National Institute for R&D in Physics and Nuclear Engineering (IFIN-HH RO))01/10/2026, 17:40
The validation campaign of the FastRICH ASIC includes a comprehensive set of laboratory and irradiation tests to assess functionality, performance, and reliability. Initial tests focus on power-up verification, interface validation (ECS, TFC), and high-speed readout integrity. Functional testing covers various internal blocks of the ASIC. Timing performance is evaluated through TDC linearity...
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Seddik Benhammadi (Science and Technology Facilities Council STFC (GB))01/10/2026, 17:40
RadPix1 is a monolithic silicon pixel sensor developed as a technology demonstrator for future LHCb tracking upgrades, targeting the Mighty Tracker and Upstream Tracker. The chip integrates four pixel flavours to explore trade offs between timing performance, hit efficiency, noise and power consumption. Building on this, RadPix1 incorporates an updated digital periphery readout derived from...
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Giacomo Fedi (Imperial College (GB))01/10/2026, 17:40
A system-level validation of the Phase-2 CMS Outer Tracker has been performed using a cosmic telescope (C-rack) integrating multiple detector ladders and a full ATCA-based readout chain. Each ladder hosts 12 2S modules, while some PS modules were added and operated in a non-final geometry. The setup implements the final powering scheme and data acquisition system, enabling a realistic slice...
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Krzysztof Cieśla (AGH University of Krakow (PL))01/10/2026, 17:40
An intermediate 48 V to 11 V DC/DC conversion stage, located in Patch Panel 2 (PP2), constitutes a key element of the power delivery chain for the ATLAS Inner Tracker (ITk) Strip detector. The design, based on commercial off-the-shelf components, meets the detector constraints and radiation tolerance requirements. The quality control (QC) and assurance (QA) procedures are in place, including...
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Muhammad Bilal Kiani (Universita e INFN Torino (IT))01/10/2026, 17:40
The High-Luminosity LHC (HL-LHC) upgrade requires a complete redesign of the CMS Drift Tube (DT) electronics to meet increased trigger rate and bandwidth demands. A new architecture minimizes on-detector processing while transferring data handling to back-end systems via high-speed optical links. The On-detector Board for Drift Tubes (OBDT) is the core component of compact on-detector...
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Bojan Markovic (SLAC National Accelerator Laboratory (US))01/10/2026, 17:40
Highly granular timing detectors are required to achieve scientific breakthroughs across HEP, NP, BES, and FES. To enable the development of these detectors, 3D-intgration between advanced sensor wafers and scaled CMOS technology nodes is required but is currently cost-prohibitive for use in scientific applications. Closing this technology gap is the joint SLAC, FNAL and LLNL effort pursuing...
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Willy Perrin (Centre National de la Recherche Scientifique (FR))01/10/2026, 17:40
This work reports the initial characterisation of the SPARC (Sensor Pixel Asynchronous Readout CMOS) prototype, investigating the feasibility of asynchronous readout logic in pixel matrices. SPARC is a monolithic active pixel sensor (MAPS) featuring a readout architecture based on locally interconnected asynchronous N:1 arbiters with fixed priority, enabling time-stamping in the 10 ns range....
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Amrutha Samalan (Paul Scherrer Institute (CH))01/10/2026, 17:40
The CMS Inner Tracker (IT) pixel detector is a key component of the Phase-2 upgrade, designed to operate under the extreme radiation levels and occupancies expected at the High-Luminosity LHC. This talk will present validation studies of IT pixel modules, focusing on the optimisation of CROC tuning parameters and their impact on threshold uniformity, noise performance, and detector response....
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Bowen Xu01/10/2026, 17:40
Pixel detectors with high spatial and temporal resolution are essential for future high-rate experiments such as the FCC. VertexPix1 is an HV-CMOS pixel detector prototype in 130 nm SiGe BiCMOS technology from IHP, featuring a 20×10 pixel matrix with 50 µm pitch. It integrates, for the first time, a deep p-well enabling in-pixel charge-sensitive amplifier with bipolar input and CMOS...
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Jonas Malte Ronsch (Technische Universitaet Dortmund (DE))01/10/2026, 17:40
The Mighty-Tracker is the Upgrade II main tracking detector of the LHCb experiment.
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The inner region of the detector will be instrumented with approximately $8\,\mathrm{m}^{2}$ of high voltage active pixel sensors (HVMAPS) called MightyPix. The functionality and performance of each sensor needs to be verified before being assembled into modules. To construct the detector about $58000$... -
Geoffrey Christian Galbit (Centre National de la Recherche Scientifique (FR))02/10/2026, 09:00
Machine learning will play a key role in the next generation of DAQ architectures, particularly through hardware-based solutions. However, methods deployed will have to meet very specific simplicity and robustness requirements.
pyml2fpga is a Python package of modules designed to transform a machine learning model into a VHDL IP that can be integrated into an FPGA firmware. The approach...
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Kotaro Chiba (Nagoya University (JP))02/10/2026, 09:00
Radiation tolerance of commercial SFP+ transceivers (SFP-10GSR-85, FS) was evaluated for detector readout in high-energy physics experiments. Total Ionizing Dose (TID), Non-Ionizing Energy Loss (NIEL), and Single Event Effects (SEE) tests were performed using gamma rays, neutrons, and high-energy hadrons, respectively. No significant degradation was observed up to 64 Gy, 2.0×10$^{13}$...
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Mahdi Zahedi02/10/2026, 09:20
Pixel detectors are used in a wide range of applications, where requirements continually evolve. Conventional fixed-function readout ASICs lack the flexibility to adapt to new processing needs. This work evaluates a programmable readout approach using a virtual prototyping methodology, integrating an open-source PULP RISC-V SoC model with the pixel readout chip model for on-detector data...
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Cort Thoreson (Northeastern University (US))02/10/2026, 09:20
The High-Luminosity Large Hadron Collider will deliver increased luminosity, pileup, and radiation levels, requiring a full replacement of the CMS Electromagnetic Calorimeter on-detector electronics. The final versions of the very front-end, front-end, and low voltage regulator cards are tested at CERN's CHARM mixed-field facility and the PSI proton irradiation facility to validate the full...
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Ms Tatiana Selezneva (KIT - Karlsruhe Institute of Technology (DE))02/10/2026, 10:10
A firmware-based luminosity measurement approach using stub counting in CMS Outer Tracker (OT) is presented. A dedicated histogramming module has been implemented in OT Data, Trigger and Control (DTC) firmware to process Level-1 trigger primitives at the full 40 MHz bunch-crossing rate. This enables zero-bias luminosity and background measurements with full per-bunch-crossing statistics. The...
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Prof. Attilio Andreazza (Università degli Studi e INFN Milano (IT))02/10/2026, 10:10
The study of Single Event Upsets (SEU) for the ATLAS ITk Pixel front-end (FE) is crucial for reliable detector operation. In early prototypes, SEU occurring at high data rate could block the FE readout until a reset is given.
Two SEU campaigns were carried out at the Centro Nazionale Adroterapia Oncologica with a 228 MeV protons beam, reaching the hit rate of the innermost ITk pixel layer,...
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Pelayo Leguina (Universidad de Oviedo (ES))02/10/2026, 10:30
Modern Level-1 trigger firmware for the HL-LHC integrates tens of HLS and RTL modules into fixed-latency FPGA pipelines, where manual wiring, latency alignment, and verification create major engineering risk. We present ARC (Algorithm Runtime and Contract framework), a plugin-agnostic, contract-driven toolchain that automates top-level RTL generation, static latency checking, and...
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Leyre Flores Sanz De Acedo (CERN)02/10/2026, 10:30
The Large Hadron Collider operates thousands of superconducting magnets that require quench detection electronics to protect them when a sudden loss of superconductivity occurs. Electronic boards are installed throughout the tunnel and must withstand the radiation from accelerator operation. During Long Shutdown 3, several will be upgraded or deployed to meet higher radiation levels in the...
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Steffie Ann Thayil (CERN)System - System Design, Description and OperationPoster
The High Granularity Timing Detector (HGTD) will be installed in the ATLAS experiment as part of the Phase-II upgrade for the High Luminosity Large Hadron Collider (HL-LHC). It will mitigate pile-up effects in the forward region and measure luminosity on a per-bunch basis. The HGTD consists of 8032 modules, each comprising Low Gain Avalanche Detectors (LGADs) bump-bonded to front-end ASICs...
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