Speaker
Description
ALTIROC-A is the front-end readout ASIC of the ATLAS High-Granularity Timing Detector (HGTD). Its large-scale production requires reliable wafer-level screening before dicing and module assembly. This contribution presents the ALTIROC-A wafer probing campaign, focusing on measured performance, including TDC and jitter characterization, wafer-to-wafer yield spread, and the constraints relevant to large-scale quality control. In the current pre-production campaign, 16 wafers have been probed at IHEP, with an average yield of about 78% under the present acceptance criteria. The contribution addresses the probing-related effects that influence chip qualification and the definition of robust screening rules for production.
Summary (500 words)
ALTIROC-A is the front-end readout ASIC of the ATLAS High-Granularity Timing Detector (HGTD). Large-scale production of HGTD readout ASICs requires wafer-level probing before dicing and module assembly. Wafer probing provides the basis for chip screening, process follow-up, and production quality assurance. Common probing tests and pass criteria have been established across the participating sites in order to ensure comparable results and consistent chip-selection decisions.
This contribution presents the ALTIROC-A wafer probing campaign with emphasis on measured performance distributions, wafer-level yield, and the practical limitations affecting large-scale testing. The current pre-production dataset provides the first large-scale evaluation of the probing strategy. In the pre-production stage, 20 wafers were available, among which 16 were probed at IHEP. Using the present acceptance definition, the average yield is about 78%, with wafer-by-wafer values ranging from 62% to 85%. The probing workflow has been progressively automated, reducing the average test time to about 13 hours per wafer, corresponding to about 6.5 minutes per ASIC, and enabling overnight operation.
In addition to standard functional tests, precise analog measurements are performed at wafer level to characterize the timing path of the 225 pixels. These measurements include Time-to-Digital Converter (TDC) calibration and jitter-related observables derived under realistic operating conditions using an LGAD-like calibration signal. They provide a more discriminating evaluation of ASIC performance and contribute significantly to the final chip qualification. At the same time, these observables are intrinsically sensitive to the experimental setup and probing conditions, which makes the final yield dependent not only on clearly non-functional chips but also on the stability and reproducibility of the measurement environment.
The campaign has shown that chip qualification is influenced by both intrinsic ASIC performance and probing-related effects. The dominant limitations identified so far are associated with contact quality, setup stability, and measurement reproducibility. These effects have a direct impact on the robustness of acceptance criteria and on the interpretation of wafer-level yield. The significance of this work lies in the establishment of a production-oriented framework for ASIC qualification at wafer level, combining performance measurements, automated test execution, and progressively consolidated screening rules for large-scale quality control.