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Description
In this work we report on the first results from a Shunt LDO (SLDO) for use in the serial powering chain of staves at the Electron Ion Collider (EIC). The device is designed in a 110nm CMOS technology and has been tested for load currents from 40mA to 900mA over an output voltage range of 1.0 to 1.4V. Tests are being carried out at temperatures from -20 to 105 degrees Celsius. First serial powering chains have also been constructed. Here we will report on these tests. We also report on the integration of the SLDO into a larger ASIC.
Summary (500 words)
The Electron Ion Collider (EIC) plans to use of smaller version of the MOSAIX chip [1] for its outer barrel layers [2]. However, MOSAIX was designed for use as a single unit in the inner barrel, and using it in multi-chip staves requires adaptation in order to reduce the amount of service cabling. This mostly involves converting parallel power and interface connections to serial versions. Since this implies serial powering, the small negative back bias required by MOSAIX must also now be generated individually for each chip, relative to the local ground.
The original intention was to integrate these functions into the edited MOSAIX. However, practical considerations now require placing them in a separate chip - the “AncASIC” - which will support the MOSAIX derived device (Figure 1). In this work, we will describe work on the SLDO for the AncASIC, and briefly discuss work on the AncASIC itself.
The SLDO concept is well known [3], and in a previous work, we described the design of an SLDO suited for the EIC application [4]. This design has now been fabricated (Figure 2), and here we report on the first test results.
Early testing has involved checking the performance of the device over a range of load currents. The SLDO includes an onboard DAC to adjust the output level, and tests so far have checked this can vary the output voltage across the full range of load currents (Figure 3). Performance has been tested at -20 and 27 degrees Celsius, and efforts are underway to test at 60 and 105 degrees as well.
The SLDO also includes a tri-state output feature. This can be operated in two ways. It can be controlled manually, in which case it is used for power sequencing of connected loads, and it can be triggered automatically when an overcurrent situation in the load is detected. The tri-state capability has been tested, and the results are shown in Figure 4.
Further detailed characterisation of the individual SLDO is ongoing, and will include performance tests at higher temperatures, radiation testing and PSRR evaluation.
Alongside this individual characterisation, a first serial powering chain has been constructed to allow evaluation of the device in its intended operating condition. This is working well and initial results are shown in Figure 5.
Aside from testing, work is currently underway to integrate the SLDO into the more complex Ancillary ASIC needed to support the EIC-LAS in the staves and discs. An outline plan of the AncASIC is shown in Figure 6.
References
[1] Development of the MOSAIX chip for the ALICE ITS3 Upgrade, P.V. Leitao, TWEPP 2024, https://doi.org/10.1088/1748-0221/20/06/C06001
[2] Development of a Silicon Vertex and Tracking Detector for the Electron-Ion Collider, L. Gonella, VERTEX 2023, https://doi.org/10.22323/1.448.0038
[3] Serial Powering Optimization for CMS and ATLAS Pixel Detectors within RD53 Collaboration for HL-LHC: System Level Simulations and Testing, Orfanelli, S et al, TWEPP 2017, https://doi.org/10.22323/1.313.0055
[4] A Shunt-LDO for the Electron Ion Collider in a 110nm CMOS Process, Sedgwick, I et al, TWEPP 2025, https://doi.org/10.1088/1748-0221/21/03/C03031