28 September 2026 to 2 October 2026
Castelldefels, Barcelona, Spain
Europe/Zurich timezone

Anomalies and criticalities discovered in the bPOL12V_V6 DC-DC converter: causes and implications.

1 Oct 2026, 09:00
16m
Auditorium

Auditorium

Oral Power - Power, Grounding and Shielding Power

Speaker

Antonio Ocarino

Description

bPOL12V_V6 is the production-grade version of a radiation-tolerant DC-DC buck converter designed in a commercial 350 nm high-voltage CMOS technology for HL-LHC front-end electronics supply, with over 100k units manufactured. In July 2025, a critical failure mode was identified during ATLAS ITk stave/petal testing: upon re-enabling after a post-irradiation time spent biased but disabled, the converter’s output voltage rose beyond nominal value. The root cause was identified as a parametric degradation in PMOS transistors involved in driving one of the power switches. Additional, less critical anomalies were also identified. Causes, implications, and mitigation strategies for all these issues are presented.

Summary (500 words)

The bPOL12V_V6 is a radiation-hard, Point-Of-Load DC/DC buck converter implemented in a 350 nm high-voltage CMOS technology. Designed to deliver output voltages between 0.6 V and 3.5 V from inputs up to 12V, it was developed to supply front-end electronics for the HL-LHC upgrade, targeting operation up to 80 Mrad of Total Ionizing Dose (TID), displacement damage fluence of 5e15neq/cm2, and temperatures ranging from −40◦C to +80◦C.

In July 2025, during qualification testing of ATLAS Inner Tracker staves and petals irradiated to 70 Mrad with a Co60 source, the converter exhibited a catastrophic failure mode.
When the converter was held biased but disabled, for a time ranging from tens of minutes to tens of hours, post-irradiation and subsequently re-enabled, the output voltage rose uncontrollably beyond specification, causing irreversible damage to connected front-end ASICs. This phenomenon, termed "sudden failure", has not been observed for converters irradiated up to 3Mrad of TID and is strongly accelerated at low temperatures.

The root cause was identified as Hot Carrier Injection (HCI)-accelerated post-irradiation annealing asymmetry within a PMOS current mirror in the level shifter driving one of the power transistors. The two PMOS devices in the mirror experience asymmetric bias during the disabled state (stress-state), causing their TID-induced threshold voltage shifts to anneal at different rates. Upon re-enabling the converter, the resulting current imbalance in the level-shifter forces unintended activation of the high-side switch, effectively shorting the output rail to the input voltage. The stress time required to trigger the failure ranges from few minutes to days and is strongly affected by the dose and temperature during the stress state.

The investigation aimed at understanding and resolving this issue uncovered also other anomalies, although less severe in terms of impact on operation:
1. Cross-conductions at startup:
A logic bug causes the high-side level shifter to slow when the PWM on-time falls below ~20 ns during startup, producing transient cross-conduction between Vin and GND due to simultaneous activation of high-side and low-side switches.
2. Rebound of the Vout at turn-off:
Depending on input voltage slew rate and load conditions, the converter output can overshoot briefly above the nominal set-point during power-down sequences.
3. Shift of linear regulators‘output:
Internal linear regulators, referenced to a DTMOS-based bandgap, exhibit an output voltage increase due to the TID-induced threshold voltage shift of the NMOS that determines it. The effect worsens with annealing, and its rate depends on temperature, but remains within technology specification.
4. Ton limitation:
During Cobalt-60 irradiations without active cooling, it was observed that the circuit’s overcurrent protection may be triggered, resulting in a reduction of the output voltage.
5. Early-enable:
When the Enable pin is driven through a resistive divider connected to the input voltage, the converter may enable at lower-than-expected voltages, depending on temperature and the Vin slew rate.

Given the scale of deployment across HL-LHC sub-detectors, these findings carry significant implications for system-level reliability. The causes, implications and suggested mitigation procedure for the above-mentioned issues will be presented.

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