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Description
We present the designs and test results of a 2.56 Gbps Clock and Data Recovery ASIC fabricated in a 55 nm CMOS technology. The ASIC mainly consists of a bang-bang phase detector, a charge pump circuit, a low-pass filter and a LC-VCO circuit. The two-step capacitor tuning structure and a novel capacitor array unit are adopted in the LC-VCO circuit. The test results show that the ASIC outputs the 2.56 GHz clock with a phase noise of -110 dBc/Hz at 1 MHz and a rms jitter of 857 fs. The detailed design and results will be reported at the workshop.
Summary (500 words)
The Clock and Data Recovery (CDR) circuit is one of the most crucial ASIC module design in the high-speed serial data transmission scenario, especially considering the extensive applications of high-speed optical communication and high-speed SerDes systems in the HEP front-end readout nowadays. It receives a pair of high-speed serial input data, recovers the clock signal from the data and offer the high-quality clock signal for the data resampling with appropriate timing.
This paper presents the design and the test results of a low jitter 2.56 Gbps reference-less CDR ASIC based on a commercial 55nm CMOS technology. The CDR ASIC consists of an input equalizer stage, a bang-bang phase detector (BBPD), a charge pump circuit (CP), a low-pass filter (LPF), a LC voltage-controlled oscillator (LC-VCO) circuit and a SPI module. The input equalizer stage adopts a 5-step continuous-time linear equalizer (CTLE) structure to compensate the high frequency loss from the system level including PCB traces, bonding wires and pads. The CTLE boosts maximum up to 9.8 dB at 7 GHz while providing a DC gain of 4.7 dB. The BBPD is used to detect the phase difference between the input data jump edge and sampling clock. To obtain low leakage current and reduce dynamic mismatch, two feedback operational amplifiers are employed in the charge pump circuit. To obtain a reasonable frequency range and an optimized Q factor performance, the two-step capacitor tuning structure and the novel capacitor array unit are adopted in the LC-VCO circuit. The two-step (coarse-fine) capacitor tuning structure consisting of the varactors and the capacitor array is adopted in the LC-VCO.
The CDR ASIC has been fabricated in a 55 nm CMOS process. The phase noise test results show that the CDR ASIC outputs the 2.56 GHz clock with a phase noise of -110 dBc/Hz at 1 MHz offset and a rms jitter of 857 fs. The logic test results show that the recovered 2.56 Gbps data is correct and the BER less than 10−12 is achieved in all tests. The detailed design and results will be reported at the workshop.