-
Miroslaw Firlej (AGH University of Krakow (PL))01/10/2026, 17:40ASICPoster
The design and measurement results of a prototype high-speed serialiser and transmitter fabricated in CMOS 65 nm technology are presented. The serialiser, with an architecture based on a multi-phase PLL clock generator, is designed to serialise digital data from multi-channel analogue-to-digital converters or other digital inputs. It outputs a serial data stream of up to 10 Gb/s, with 8b/10b...
Go to contribution page -
Oi Ying Wong (Nikhef National institute for subatomic physics (NL))01/10/2026, 17:40ASICPoster
A high-resolution, monotonic DAC is essential for precise global threshold setting in the Picopix pixel detector chip, enabling accurate S-curve extraction and reliable control of effective per-pixel thresholds after trimming. Conventional R-string or current-steering architectures scale poorly in area or suffer from non-monotonicity due to device mismatch. This work presents a 12-bit ∑∆DAC in...
Go to contribution page -
Xiongbo Yan (Institute of High Energy Physics)01/10/2026, 17:40ASICPoster
Addressing the need for higher data rates in high-energy physics readout links, this work introduces a four-level pulse-amplitude-modulation (PAM4) transmitter with a 2-tap feed-forward equalizer (FFE), implemented in a 55-nm CMOS technology. An initial version employs a PRBS pattern generator (2^7-1) instead of a silicon-proven 16:1 serializer to save area and validate the PAM4...
Go to contribution page -
Mr Longkai Li (Central China Normal University)01/10/2026, 17:40ASICPoster
We present designs and test results of a 25 Gbps VCSEL driving ASIC fabricated in a 55 nm CMOS technology for detector front-end readout. This ASIC proposed a new output driver design using the double-feedforward capacitor compensation, combined with the T-coil technique (customized on-chip inductor) and the adjustable FFE pre-emphasis structure to achieve 25 Gbps bandwidth in 55 nm...
Go to contribution page -
Xiaoting Li (IHEP)01/10/2026, 17:40ASICPoster
High‑resolution time‑to‑digital converters (TDCs) are essential for time-of-flight positron emission tomography and high-energy physics experiments. We present a TDC core (xpdTDC) implemented in a 55-nm CMOS process. The architecture employs a ring‑oscillator‑based delay line coupled with a passive timing interpolation circuit, using a circular interpolation strategy to achieve a 5.2-ps...
Go to contribution page -
Alexander Friedrich Elsenhans (KIT - Karlsruhe Institute of Technology (DE))01/10/2026, 17:40ASICPoster
A compact single-shot time-to-digital converter (TDC) implemented in 16 nm FinFET technology is presented for ultra-fine timing in future pixel detector readout systems and 3D-integrated architectures. The design employs a gated ring oscillator combined with a high-speed cycle counter and is implemented exclusively using standard cells. Measurements show an effective LSB size of approximately...
Go to contribution page -
Prof. Di Guo (Central China Normal University)01/10/2026, 17:40ASICPoster
We present the designs and test results of a 2.56 Gbps Clock and Data Recovery ASIC fabricated in a 55 nm CMOS technology. The ASIC mainly consists of a bang-bang phase detector, a charge pump circuit, a low-pass filter and a LC-VCO circuit. The two-step capacitor tuning structure and a novel capacitor array unit are adopted in the LC-VCO circuit. The test results show that the ASIC outputs the...
Go to contribution page -
Datao Gong (Fermi National Accelerator Lab. (US))01/10/2026, 17:40ASICPoster
A low-power, high-precision TDC for ePIC timing detector readout is presented in a 65 nm CMOS process. The design features a self-calibrated architecture, providing a compact implementation and PVT robustness suitable for pixel readout. Time resolution is enhanced using a multi-timestamp reconstruction technique with a programmable range of 2 to 65 timestamps. Using triangular-weighted...
Go to contribution page -
Joaquim Pinol Bel (IFAE)01/10/2026, 17:40ASICPoster
This contribution presents a high-resolution TDC architecture designed for high-density timing applications. While initially developed for the CACTUS R&D timing detector, the design offers a scalable solution for any system requiring sub-10 ps precision with minimal area overhead. The TDC is based on a digital un-tuned oscillator built with 64 inverters, providing a time resolution of 8 ps....
Go to contribution page -
Mr 铮 王 (中国科学院高能物理研究所)01/10/2026, 17:40ASICPoster
This report presents LATRICi, a novel pulse-interleaved time-to-digital converter (TDC) implemented in a 55nm CMOS process. As an evolution of the initial version based on an event-driven ring oscillator architecture, the proposed design enhances resolution and reduces mismatch through optimized delay cells and a novel latch-pulse-interleaved circuit, achieving an average unit delay of 22.5 ps...
Go to contribution page -
wangna@ihep.ac.cn wangna01/10/2026, 17:40ASICPoster
The Polarimetry Focusing Array (PFA) of the planned eXTP mission employs three identical X-ray imaging telescopes for polarimetry in the 2–8 keV band. Each detector integrates a radiation sensor with a dedicated ASIC for precise charge readout. We present a self-triggered ASIC with reconfigurable event-driven windows and a two-stage analog readout architecture. A 70×60 pixel prototype (50 μm...
Go to contribution page -
Mark Pesaresi (Imperial College (GB))01/10/2026, 17:40Production - Production, Testing and ReliabilityPoster
A burn-in campaign of the Phase-2 CMS Outer Tracker backend electronics is performed on pre-production Serenity and Apollo boards prior to deployment. The setup consists of two fully populated ATCA crates, with all optical links active simultaneously, enabling operation in a realistic and highly interconnected environment. Particular emphasis is placed on validation of optical interfaces...
Go to contribution page -
Adrien VERPLANCKE01/10/2026, 17:40ASICPoster
EICROC is a readout ASIC for AC-LGAD sensors developed for the future Electron-Ion Collider at Brookhaven. It targets precise timing and accurate vertex reconstruction.
Go to contribution page
Designed as a System-on-Chip, it processes signals through two parallel paths: a fast path for Time-of-Arrival and a slow path for charge measurement, both with on-chip digitization.
The first prototype, EICROC0, and its... -
Matteo Magherini (CERN)01/10/2026, 17:40Production - Production, Testing and ReliabilityPoster
The CMS Phase-2 Outer Tracker is progressing toward large-scale system validation ahead of LS3 installation. Multi-module mechanical structures— ladders, rings, planks, and dees— assembled and characterized at integration centers, are brought together into higher-level structures and tested at the Tracker Integration Facility at CERN with final services and complete readout architecture. Noise...
Go to contribution page -
Dr Ke WANG (Institute of High Energy Physics，Chinese Academy of Sciences)01/10/2026, 17:40ASICPoster
This paper presents a low-noise readout application-specific integrated circuit（ASIC） optimized for three-dimensional position-sensitive cadmium–zinc–telluride (CZT) detectors. Specialized cathode channels are incorporated to accommodate the large planar cathodes of pixelated detectors. Simulation results indicate an anode noise of 64$\mathrm{\ }$$e^-$+8 $e^-$/pF and a cathode noise of...
Go to contribution page -
Joel Daricou (CERN)01/10/2026, 17:40Production - Production, Testing and ReliabilityPoster
The qualification of radiation-tolerant DC/DC converters for high-energy physics experiments requires reliable, reproducible, and easily deployable test infrastructures across multiple external facilities. Issues identified in late 2025 with the bPOL12 converter highlighted limitations of existing test setups, triggering at CERN the design of a universal test platform, the DC/DC Universal Test...
Go to contribution page -
Luca Ghislotti (INFN Pavia & University of Bergamo)01/10/2026, 17:40ASICPoster
This contribution presents the design and characterization of an analog channel developed in a 65 nm CMOS process. Designed for the readout of large-area silicon-strip detectors, it integrates a low-noise, wide dynamic range charge-sensitive amplifier (CSA) followed by a filtering stage for signal-to-noise optimization. Dynamic signal compression, achieved via a novel dynamic-threshold MOSFET...
Go to contribution page -
Dr Huaishen LI (IHEP)01/10/2026, 17:40ASICPoster
Abstract: SIPAC is a 4-channel ASIC prototype for SiPM readout in CEPC's ECAL, HCAL, LumiCal, and Muon detector. The chip integrates preamplifier, shaper, ADC, TDC, and serializer. A DAC calibrates SiPM gain, with each channel featuring a dedicated calibration path for single-photon calibration. The chip has been taped-out, and silicon testing is expected to be completed in August....
Go to contribution page -
Vladimir Gromov (Nikhef National institute for subatomic physics (NL))01/10/2026, 17:40ASICPoster
A new silicon tracker detector (ITS3) will be installed in the ALICE Inner Tracking System during the LHC Long Shutdown 3 [1]. We have developed a 10.24 Gbps Data Serializer and Wireline Transmitter (GWT-PSI) circuit for the detector readout. A 16-to-1 multiplexer architecture achieves low power consumption and avoids high-frequency (> 640MHz) clock signals in the circuit. A power-supply...
Go to contribution page -
Gabriele Ciarpi (CERN)01/10/2026, 17:40ASICPoster
This work presents a radiation-tolerant, multi-stage serializer designed in 28 nm CMOS, aggregating 80 streams into a single 25.6 Gb/s channel. The architecture employs a multi-stage (80:16, 16:4, and 4:1) approach featuring a quad-rate output stage and integrated pre-emphasis taps to compensate for channel losses. By applying radiation-hardening techniques only to critical control signals and...
Go to contribution page -
Dr Yang Zhou (Institute of High Energy Physics, CAS, Beijing, China)01/10/2026, 17:40ASICPoster
Driven by LHCb Upgrade II Upstream Tracker and CEPC Inner Tracker, the COFFEE series of HV-MAPS is developed in a 55 nm process. It targets <5 ns time resolution, ~10 μm spatial resolution, and <200 mW/cm² power consumption at a hit density up to 100 MHz/cm². The small-scale COFFEE3 prototype integrates two independent architectures: NMOS-only in-pixel circuitry, and CMOS in-pixel TDC, to meet...
Go to contribution page -
Alberto Arcusa Puente (Aragon Institute of Technology Itainnova (ES))01/10/2026, 17:40Power - Power, Grounding and ShieldingPoster
This work presents an electromagnetic compatibility (EMC) characterization focused on noise sensitivity in the data acquisition reference system and the Micromegas detector of the BabyIAXO prototype. The dominant noise coupling mechanisms affecting the system baseline are identified and analyzed. We ensure measurements in an EMC-clean environment, by using the ITA anechoic chamber. We propose...
Go to contribution page -
Flavio Loddo (Universita e INFN, Bari (IT)), Giuseppe De Robertis (Universita e INFN, Bari (IT))01/10/2026, 17:40ASICPoster
In this work the design of FATIC4, a new readout ASIC in CMOS 130 nm for the µ-RWELL-based detectors proposed for LHCb upgrade II muon system, is described. A previous version of the ASIC, FATIC3, was successfully tested in laboratory and during test beam campaigns with µ-RWELL-prototypes. Its main limitation was its dead time of about 1us, not compatible with the expected signal rate of about...
Go to contribution page -
Joelle Savelberg (Rheinisch Westfaelische Tech. Hoch. (DE))01/10/2026, 17:40Power - Power, Grounding and ShieldingPoster
The bPOL48V is a point-of-load DC-DC buck converter developed at CERN and characterised at RWTH Aachen University within the DRD7 program. Targeting future high-energy physics experiments, it reduces cable power losses by converting a 48V input to a 5-24V output using a GaN-based power stage.
Go to contribution page
Currently, CMS silicon strip modules use DC-DC converters to convert 12V to 1.25V in a two-step... -
Iain Sedgwick (Science and Technology Facilities Council STFC (GB))01/10/2026, 17:40ASICPoster
In this work we report on the first results from a Shunt LDO (SLDO) for use in the serial powering chain of staves at the Electron Ion Collider (EIC). The device is designed in a 110nm CMOS technology and has been tested for load currents from 40mA to 900mA over an output voltage range of 1.0 to 1.4V. Tests are being carried out at temperatures from -20 to 105 degrees Celsius. First serial...
Go to contribution page -
Jakub Moron (AGH University of Krakow (PL))01/10/2026, 17:40ASICPoster
The design and results of mass tests and detailed characterisation of the second fabrication run of a SoC readout ASIC, called FLAXE, are presented. The FLAXE has been developed for the ECALpelectromagnetic calorimeter at the LUXE experiment. The ASIC consists of 32 channels, each comprising a programmable gain preamplifier, a fully differential shaper, and a 10-bit SAR ADC working nominally...
Go to contribution page -
Sara Portero Castillo (Universitat de Barcelona)01/10/2026, 17:40ASICPoster
Timing resolution is of paramount importance in Particle Physics Experiments, and many other time-of-flight systems, such as Positron Emission Tomography (PET) LIDAR or mass spectrometry, since it directly translates to better image quality. This work will study what are the most relevant parameters (noise, bandwidth, parasitics, etc.) of a Front End readout circuit to optimize timing...
Go to contribution page -
Jesus Pena Rodriguez (Bergische Universität Wuppertal)01/10/2026, 17:40ASICPoster
Analog-to-Digital converters (ADCs) have been widely used to measure signal charge and amplitude due to their precision, measurement range, and linearity. Nevertheless, power consumption, data volume, and bandwidth make them unfeasible for the next generation of high-energy physics experiments. Time-over-Threshold (ToT) circuits offer simplicity, low power consumption, ease of integration, and...
Go to contribution page -
Jia WANG (Northwestern Polytechnical University)01/10/2026, 17:40ASICPoster
Cadmium Zinc Telluride (CZT) detectors are featured as high energy resolution and room-temperature working. Nevertheless, short lifetime of holes in CZT crystals results in energy spectrum broadening for high-energy particles. To address this issue, precise depth-of-interaction (DOI) is required to correct the energy spectrum.
Go to contribution page
This report presents the design of a multi-channel... -
Miquel Ribalda Galvez (University of Barcelona (ES))01/10/2026, 17:40ASICPoster
This work presents the first silicon results of a 12-bit low-power SAR ADC fabricated in 65 nm CMOS for multi-channel detector readout applications. The design targets >40 MS/s operation, sub-mW power consumption, and a compact area (0.036 mm²). It uses a fully differential architecture, a segmented capacitive DAC, a dynamic comparator, and asynchronous control logic to maximise efficiency. A...
Go to contribution page -
Dr Dirk Wiedner (Technische Universitaet Dortmund (DE))01/10/2026, 17:40Production - Production, Testing and ReliabilityPoster
The second upgrade of LHCb is aiming at an instantaneous luminosity of $1.0\times 10^{34}cm^2/s.$ The current downstream tracking system is replaced by an inner pixel tracker and an outer scintillating fibre tracker. The $8\,m^2$ inner pixel detector is based on $4\,cm^2$ sized High Voltage Monolithic Active Pixel Sensors (HVMAPS). Five HVMAPS are mounted on one module. For the efficient...
Go to contribution page -
Mr Yuanhong Jiao (Northwestern Polytechnical University)01/10/2026, 17:40ASICPoster
This paper presents a system-level modeling methodology for current-steering DACs in front-end readout ASICs using User-Defined Nettypes (UDN). To overcome the limitations of SPICE (low speed) and traditional wreal (lack of loading effects), a VIZ (Voltage-Current-Impedance) structural UDT (User-Defined Type) is implemented with User-Defined Resolution (UDR) based on nodal admittance analysis....
Go to contribution page -
Laurent Royer (Université Clermont Auvergne (FR))01/10/2026, 17:40Power - Power, Grounding and ShieldingPoster
The ATLAS HGTD detector must meet low-noise requirements at the system level to achieve a time resolution of 50 ps per hit during the HL-LHC operations. Consequently, an optimal grounding and shielding strategy is required, which must be evaluated and refined throughout the detector’s development. Measurements on the demonstrator setup revealed excessive common mode conducted noise on power...
Go to contribution page -
Ahmed Qamesh (Karlsruher Institut für Technologie (KIT))01/10/2026, 17:40Production - Production, Testing and ReliabilityPoster
The CMS Phase-2 upgrade introduces a new high-granularity calorimeter (HGCAL). The HGCAL back-end will use about 300 Serenity-S1 FPGA boards using Samtec FireFly electro-optical modules with a link speed of up to 25 Gb/s. Existing production tests only validate the high-speed links via copper loopback cables. We present an Optical Acceptance Test (OAT) framework providing comprehensive link...
Go to contribution page -
Krzysztof Piotr Swientek (AGH University of Krakow (PL))01/10/2026, 17:40ASICPoster
This contribution outlines the design of the novel PACIFIC++ readout ASIC in CMOS 65 nm for LHCb Mighty-SciFi for LHCb Upgrade II. The architecture incorporates low-noise analogue front-end, amplitude and timing measurements using ADC and TDC embedded in each channel, followed by on-chip data processing and clustering, to meet the stringent speed and power requirements of next-generation...
Go to contribution page -
Mr Alberto López (ICCUB)01/10/2026, 17:40ASICPoster
This work presents the analog design and performance of the ICECAL65 ASIC, a 4-channel ASIC developed in a 65 nm CMOS technology specifically designed to be included in the Front-End Board (FEB) of the LHCb Upgrade II calorimeter. This ASIC enables the continuous readout of Photomultiplier Tubes (PMTs) with a 12-bit resolution and a power consumption of ~ 50 mW per channel. The ASIC is...
Go to contribution page -
Llorenç Fanals-i-Batllori01/10/2026, 17:40ASICPoster
This work presents a cryogenic mixed-signal ASIC for noble-liquid time projection chambers (TPCs) targeting next-generation dark matter experiments such as XLZD \cite{xlzd2024}. Fabricated in CMOS TSMC 28-nm technology, the single-channel prototype integrates three parallel low-input-impedance transimpedance amplifiers with gains of 1, 1/40, and 1/400 to accommodate the wide dynamic range...
Go to contribution page -
Bilal Hasan Qureshi (University of Bergen (NO))01/10/2026, 17:40Power - Power, Grounding and ShieldingPoster
The University of Bergen is involved in the design and development of the Electromagnetic Forward Calorimeter (FOCAL-E). This is a major upgrade for LHC Run 4 to the ALICE experiment at CERN. This paper presents the power board design for FOCAL-E pixel layers that provides power to the ALPIDE sensor strings connected to a transition card. The design comprises radiation-hard bPOL48V modules...
Go to contribution page -
Mr Bendik Husa (University of Bergen (NO))01/10/2026, 17:40Production - Production, Testing and ReliabilityPoster
For the planned FoCal-E subdetector in ALICE, the ALPIDE pixel modules are currently being assembled and there is a need to qualify them for use. The pixel modules are tested in three stages: isolated test, assembly test and integration test. To do this, a production test system has been adopted from the Bergen proton CT project along with changes based on experiences gained. In particular,...
Go to contribution page -
Vlad-Mihai Placinta (Horia Hulubei National Institute for R&D in Physics and Nuclear Engineering (IFIN-HH RO))01/10/2026, 17:40ASICPoster
The validation campaign of the FastRICH ASIC includes a comprehensive set of laboratory and irradiation tests to assess functionality, performance, and reliability. Initial tests focus on power-up verification, interface validation (ECS, TFC), and high-speed readout integrity. Functional testing covers various internal blocks of the ASIC. Timing performance is evaluated through TDC linearity...
Go to contribution page -
Seddik Benhammadi (Science and Technology Facilities Council STFC (GB))01/10/2026, 17:40ASICPoster
RadPix1 is a monolithic silicon pixel sensor developed as a technology demonstrator for future LHCb tracking upgrades, targeting the Mighty Tracker and Upstream Tracker. The chip integrates four pixel flavours to explore trade offs between timing performance, hit efficiency, noise and power consumption. Building on this, RadPix1 incorporates an updated digital periphery readout derived from...
Go to contribution page -
Giacomo Fedi (Imperial College (GB))01/10/2026, 17:40Production - Production, Testing and ReliabilityPoster
A system-level validation of the Phase-2 CMS Outer Tracker has been performed using a cosmic telescope (C-rack) integrating multiple detector ladders and a full ATCA-based readout chain. Each ladder hosts 12 2S modules, while some PS modules were added and operated in a non-final geometry. The setup implements the final powering scheme and data acquisition system, enabling a realistic slice...
Go to contribution page -
Krzysztof Cieśla (AGH University of Krakow (PL))01/10/2026, 17:40Power - Power, Grounding and ShieldingPoster
An intermediate 48 V to 11 V DC/DC conversion stage, located in Patch Panel 2 (PP2), constitutes a key element of the power delivery chain for the ATLAS Inner Tracker (ITk) Strip detector. The design, based on commercial off-the-shelf components, meets the detector constraints and radiation tolerance requirements. The quality control (QC) and assurance (QA) procedures are in place, including...
Go to contribution page -
Muhammad Bilal Kiani (Universita e INFN Torino (IT))01/10/2026, 17:40Production - Production, Testing and ReliabilityPoster
The High-Luminosity LHC (HL-LHC) upgrade requires a complete redesign of the CMS Drift Tube (DT) electronics to meet increased trigger rate and bandwidth demands. A new architecture minimizes on-detector processing while transferring data handling to back-end systems via high-speed optical links. The On-detector Board for Drift Tubes (OBDT) is the core component of compact on-detector...
Go to contribution page -
Bojan Markovic (SLAC National Accelerator Laboratory (US))01/10/2026, 17:40ASICPoster
Highly granular timing detectors are required to achieve scientific breakthroughs across HEP, NP, BES, and FES. To enable the development of these detectors, 3D-intgration between advanced sensor wafers and scaled CMOS technology nodes is required but is currently cost-prohibitive for use in scientific applications. Closing this technology gap is the joint SLAC, FNAL and LLNL effort pursuing...
Go to contribution page -
Willy Perrin (Centre National de la Recherche Scientifique (FR))01/10/2026, 17:40ASICPoster
This work reports the initial characterisation of the SPARC (Sensor Pixel Asynchronous Readout CMOS) prototype, investigating the feasibility of asynchronous readout logic in pixel matrices. SPARC is a monolithic active pixel sensor (MAPS) featuring a readout architecture based on locally interconnected asynchronous N:1 arbiters with fixed priority, enabling time-stamping in the 10 ns range....
Go to contribution page -
Amrutha Samalan (Paul Scherrer Institute (CH))01/10/2026, 17:40Production - Production, Testing and ReliabilityPoster
The CMS Inner Tracker (IT) pixel detector is a key component of the Phase-2 upgrade, designed to operate under the extreme radiation levels and occupancies expected at the High-Luminosity LHC. This talk will present validation studies of IT pixel modules, focusing on the optimisation of CROC tuning parameters and their impact on threshold uniformity, noise performance, and detector response....
Go to contribution page -
Bowen Xu01/10/2026, 17:40ASICPoster
Pixel detectors with high spatial and temporal resolution are essential for future high-rate experiments such as the FCC. VertexPix1 is an HV-CMOS pixel detector prototype in 130 nm SiGe BiCMOS technology from IHP, featuring a 20×10 pixel matrix with 50 µm pitch. It integrates, for the first time, a deep p-well enabling in-pixel charge-sensitive amplifier with bipolar input and CMOS...
Go to contribution page -
Jonas Malte Ronsch (Technische Universitaet Dortmund (DE))01/10/2026, 17:40Production - Production, Testing and ReliabilityPoster
The Mighty-Tracker is the Upgrade II main tracking detector of the LHCb experiment.
Go to contribution page
The inner region of the detector will be instrumented with approximately $8\,\mathrm{m}^{2}$ of high voltage active pixel sensors (HVMAPS) called MightyPix. The functionality and performance of each sensor needs to be verified before being assembled into modules. To construct the detector about $58000$...
Choose timezone
Your profile timezone: