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Description
This paper presents a system-level modeling methodology for current-steering DACs in front-end readout ASICs using User-Defined Nettypes (UDN). To overcome the limitations of SPICE (low speed) and traditional wreal (lack of loading effects), a VIZ (Voltage-Current-Impedance) structural UDT (User-Defined Type) is implemented with User-Defined Resolution (UDR) based on nodal admittance analysis. The model incorporates parameterized non-ideal factors including Pelgrom-based random mismatch and systematic gradients. Results demonstrate 10×–1000× simulation speedup over SPICE with INL and DNL information. The DAC model enables concurrent DAC and system design with efficient equivalence verification.
Summary (500 words)
In front-end readout ASIC, on-chip DACs play a critical role in providing precise threshold voltages for front-end amplifiers, which directly determines the detection accuracy and reliability of the entire system. In the ESL (Electronic System Level) design, traditional verification approaches face fundamental trade-offs: transistor-level SPICE simulation offers high accuracy but is prohibitively slow for full-chip parametric sweeps, while conventional digital or wreal modeling lacks impedance information and fails to capture loading effects, leading to incorrect node voltage calculations. The significance of DAC modeling in complex system design is its ability to verify required DAC precision at the system level in the early design stage, enabling simultaneous DAC design and system design. Ultimately, only equivalence verification between the physical DAC design and the proposed model is needed, greatly reduces design iterations and shortens the overall development cycle.
To address these challenges, we propose a VIZ-UDN (Voltage-Current-Impedance User-Defined Nettype) modeling approach compliant with IEEE Std 1800-2023 SystemVerilog. It defines a three-element port structure {V, I, Z} that transcends limitations of traditional real-number modeling. Through User-Defined Resolution functions based on nodal admittance analysis, the model automatically computes node voltages considering multiple parallel drivers and finite impedance effects, accurately reproducing the physical behavior of current-steering DACs including output impedance and loading effects. A 10-bit segmented DAC architecture is modeled with parameterized non-ideal factors: (1) Random mismatch following Pelgrom's model with configurable relative standard deviation σ (0.1%–0.5%); (2) Area scaling mechanism, where random mismatch scales with the square root of unit area, in line with the Pelgrom model; (3) Systematic linear gradients (150–300 ppm) simulating position-dependent manufacturing variations.
The modeling framework is implemented in a UVM-MS (Mixed-Signal) verification environment. A Dual-Top architecture separates the system UVM test environment from the DAC testbench, enabling seamless cross-domain observation between digital and analog signals. The verification platform includes reference models and tolerance-aware scoreboards for automated closed-loop checking of analog specifications, laying a foundation for efficient equivalence verification between the model and physical DAC design.
Simulation results demonstrate the effectiveness of the proposed methodology. For input code 10’d1, the modeled output voltage of 1.55999 mV closely matches the designed LSB step of 1.56 mV. With σ of 0.1%, the DAC exhibits an INL of about 0.05 LSB and a DNL of about 0.02 LSB. Random mismatch primarily affects DNL dispersion, while systematic gradients introduce characteristic "bow-shaped" INL errors that intensify with increasing gradient magnitude. The SV-RNM (System Verilog Random Number Modeling) approach achieves 10 to 50 times speedup for single-channel static parameter scans.
This work validates a DAC modeling approach for mixed-signal verification in ESL design. By parameterizing non-ideal effects and leveraging UDN-based real-number modeling, the methodology highlights the importance of DAC modeling in complex system design: it enables system-level verification of DAC precision early, supports concurrent DAC and system design, and reduces design iterations through efficient equivalence verification between the model and physical DAC. This significantly reduces verification cycle time while preserving accuracy essential for DAC specification validation in complex systems.