Speaker
Description
Analog-to-Digital converters (ADCs) have been widely used to measure signal charge and amplitude due to their precision, measurement range, and linearity. Nevertheless, power consumption, data volume, and bandwidth make them unfeasible for the next generation of high-energy physics experiments. Time-over-Threshold (ToT) circuits offer simplicity, low power consumption, ease of integration, and a wide bandwidth but lack precision, linearity, and dynamic range. We present a shaper circuit that improves the weaknesses of ToT systems without sacrificing performance.
Summary (500 words)
Most particle detector readouts use analog-to-digital converters (ADCs) to quantize the output signal amplitude/charge and measure the deposited energy of charged particles crossing a detector volume. This methodology requires buffer storage, depending on the sampling frequency: the higher the sampling frequency, the more precise the energy estimation, the larger the required buffer size, and the higher the power consumption, the larger the dead time, and the lower the bandwidth.
Time-over-threshold (ToT) circuits measure the time difference between the leading and trailing edges of a signal, typically a discriminator output signal. This approach significantly reduces the required buffer size, circuit complexity, and power consumption, thus improving circuit integration (ASIC implementation) and counting rates. However, ToT systems degrade energy resolution, dynamic range, and linearity.
There exist different architectures to implement analog signal discrimination for ToT measurement: comparing the input pulse signal either with a constant threshold or with a dynamic threshold and holding the maximum pulse amplitude and comparing it with a dynamic threshold. Those approaches have drawbacks, such as implementation complexity, power consumption per channel, nonlinearities, and limited detection rate.
We present a simple signal-shaping method that improves ToT determination and offers good linearity, a large bandwidth, low power consumption, and high integrability. The shaping circuit contains a fast diode that discharges a capacitor with a constant current, thereby linearizing the trailing edge of the input signal. We characterized the circuit performance with Spice simulations and under controlled experimental conditions. The three tested capacitances (47\,pF, 100\,pF, and 330\,pF) confirmed the linearization concept, with R-squared values between the linear model and the data around 0.99. The shaper precision and resolution improve with the circuit capacitance, but also the dead time. The shaper bandwidth was $\sim$150\,MHz for 47\,pF.
We implemented the circuit concept in the DIRICH readout system of the Ring Imaging Cherenkov detector of the Compressed Baryonic Matter experiment at FAIR. The DIRICH front-end electronics provides 32 individual channels of high-precision FPGA-TDC-based ToT measurement. Each channel includes a discrete transistor-based fast input amplifier with a gain of $\sim$ 30 and 4\,GHz bandwidth. Signal discrimination and the subsequent leading and trailing edge time measurements are implemented on the ECP5 FPGA, which provides timing precision better than 20\,ps (RMS). The DIRICH TDC measures the leading and trailing edges of the signal above a constant threshold set by a 16-bits Delta-Sigma DAC (Digital-to-Analog Converter) with a resolution of $\sim 0.04$\,mV. We modified one of the DIRICH channels connecting the shaper circuit. The performance of the system was tested by inputing signals from a Broadcom AFBR-S4N66P024M SiPM.