Speaker
Description
This contribution presents the design and characterization of an analog channel developed in a 65 nm CMOS process. Designed for the readout of large-area silicon-strip detectors, it integrates a low-noise, wide dynamic range charge-sensitive amplifier (CSA) followed by a filtering stage for signal-to-noise optimization. Dynamic signal compression, achieved via a novel dynamic-threshold MOSFET (DTMOS) capacitor in the CSA feedback, enables a four-decade dynamic range, allowing spectroscopy below 100 keV and charged particle detection up to 100 MeV. A bulk-driven Krummenacher circuit compensates for leakage currents up to 200 nA. Design details and comprehensive measurements of the proposed channel are reported.
Summary (500 words)
Silicon-based tracking systems, including large-area strip detectors, are widely employed in particle physics and astrophysics for particle tracking and spectroscopy. In several applications, particularly in balloon-borne and space-based experiments for indirect dark matter searches, the readout electronics must simultaneously process low-energy X-rays in the 10–100 keV range (2.7e3–2.7e4 e⁻) and charged particles depositing energies exceeding 100 MeV (2.7e7 e⁻), thus requiring a very large dynamic range. This imposes a four-decade input dynamic range on the front-end, precluding purely linear amplification. At ambient temperature, detector leakage current increases by orders of magnitude compared to operation at −40 °C, requiring tolerance to large leakage variations.
To address these challenges, this work presents an integrated analog channel developed in a commercial 65 nm CMOS technology for large-area Si(Li) detector readout, representing an evolution of a previous 180 nm design. The channel architecture comprises a charge-sensitive amplifier (CSA) processing electrons at the input, followed by a unipolar semi-Gaussian time-invariant CR-RC shaper with eight selectable peaking times (0.2–1.6 µs), providing a gain factor of 1.2. To accommodate the wide input energy range, dynamic signal compression is implemented at the preamplifier stage using a dynamic-threshold MOSFET (DTMOS) operated as a capacitor within the CSA feedback network. In this configuration, the substrate is connected to the gate, dynamically reducing the threshold voltage as the CSA output increases. This modulates the feedback capacitance, yielding an approximately bilinear transfer characteristic that maps the full four-decade dynamic range onto an output swing of about 500 mV. To address the detector leakage current, the CSA integrates an improved Krummenacher network with a bulk-driven control terminal, enabling stable operation up to 200 nA and reliable testing at ambient temperature.
Measurements were performed from −40 °C to 40 °C with detector capacitances (Cd) from 0 to 100 pF. At −40 °C and for Cd = 40 pF, the low-energy gain (Gle) is 220 µV/keV (4.97 mV/fC) and the high-energy gain (Ghe) is 1.96 µV/keV (44.3 µV/fC), yielding a compression factor (k = Gle/Ghe) of 112. In both regimes, the integral nonlinearity (INL) is below 1.5%. The channel achieves an energy resolution of 3.2 keV FWHM (379 e⁻ rms equivalent noise charge) at a peaking time of 804 ns and Cd = 40 pF. The noise increases from ~260 e⁻ (~2.2 keV) to ~670 e⁻ (~5.7 keV) over Cd = 0–100 pF, corresponding to ~4 e⁻/pF (~0.034 keV/pF). At 25 °C, the Krummenacher network compensates leakage currents up to 200 nA, maintaining k > 73 and INL < 5%. Power consumption is 4 mW per channel, below the 10 mW target. Compared to the 180 nm implementation, power, area, and noise are reduced by 52%, 73%, and 35%, respectively.
The contribution will discuss the design and architecture of the analog readout channel, focusing on the DTMOS-based signal compression and the bulk-driven charge restoration network, together with experimental results under different operating conditions and comparison with the previous generation.