Speaker
Description
The ALICE ITS3 upgrade for LHC Run 4 uses stitched wafer-scale MAPS, enabling a material budget of $0.9\%\ X_0$ per layer with bent, $50\,\mu m$ thick modules. The full-scale prototype sensor, MOSAIX, integrates power and data distribution, power-gated sensor tiles, and high-speed transmitters. System integration and performance aspects including power, electrical, optical and signal integrity characteristics is assessed using various test setups.
This presentation covers the performance of MOSAIX operation in different environments. Results from wafer probing, MOSAIX mounted on carrier boards and installed in ITS3 detector prototype setups including final cabling, power supply and readout electronics will be presented.
Summary (500 words)
As the final prototype, the ALICE ITS3 MOSAIX chip implements all features required for integration into the final detector system, such as 144 individually powered pixel matrix tiles, data transmission over $26.6\,cm$ across the length of the chip, and data aggregation and off-chip transmission via high-speed links. This level of integration enables the ultra-low material budget of $0.09\%\ X_0$ per layer, but increases complexity in testing and operation.
In traditional detector setups, the system components of sensor, data and power transmission, as well as data aggregation can be tested independently prior to testing them together. However, since MOSAIX integrates all these components in a single die, the full system can be tested only as a whole with limited access to intermediate stages via debugging pins. This increases complexity of qualification and testing and convolutes effects of the individual subsystems.
Each tile transmits a differential 160 or $80\,Mb/s$ bit stream which is buffered and re-timed up to 24 times across the chip in the so-called stitched-backbone (SBB) toward the left endcap of the chip. The drivers of the SBB can be tuned for improved signal integrity.
In the left endcap of the chip, lpGBT-based data aggregation and serialization is performed. Each link can operate at 5 or $10\,Gb/s$ with a total of eight links available per MOSAIX chip. Each serializer contains individual LDOs to achieve a stable low-noise supply voltage and a PLL/DLL pair for clock multiplication. The output is connected to VTRx+ electro-optical transmitters. In laboratory tests, it is also possible to route the high-speed channels to a readout FPGA electrically.
Chip qualification, including functional and electrical verification and yield estimation, relies on wafer probing and single-chip carrier boards in the first stage. In addition, two detector half barrels are built as qualification models, for the full ITS3 structure including flex PCB power/signal connections, optical transmission and final power/service electronics. To prepare the transition to the full model, various intermediate integration levels are tested to disentangle effects of the chip, cabling, power supply and data transmission medium. Each testing stage increases fidelity and integration complexity, revealing previously unobserved properties.
Both, the SBB and the high-speed links are sensitive to their environment via noise, jitter and crosstalk. These parameters are fundamentally dependent on the chip environment. The measurements including different parts of the system allow the deconvolution of setup related effects and the particular sources.
Initial tests on chip carrier boards show promising results for the electrical side of high-speed links. However, the SBB performs worse than expected from simulation with bit errors in the percent range. Full recovery of data integrity is possible at the expense of more power consumption. While further investigations on the SBB are ongoing, the tests for optical high-speed readout are in preparation.
This presentation will compare the results of MOSAIX operation in these distinct environments. Experience from wafer probing, chip carrier testing and full system integration will be presented and setup related effects will be analyzed and disentangled with focus on data integrity.