Speaker
Description
This study proposes a 1D Convolutional Neural Network (CNN) architecture designed for real-time particle hit detection, moving beyond traditional rigid triggering thresholds. By processing continuous data streams, including high-noise environments, our model demonstrates superior sensitivity in low Signal-to-Noise Ratio (SNR) regimes and pile up events. We demonstrate that this approach successfully identifies particle signals and provides precise temporal metadata in real time, offering a robust alternative to conventional signal processing methods. Performance was evaluated on a scintillating muon detector.
Summary (500 words)
In this project, single channel triggering is achieved with a CNN running on a CAEN DT2740 digitizer. The system leverages the Zynq UltraScale+ xczu19eg to process 64-channel, 16-bit analog-to-digital conversion at a sampling rate of 125 MS/s. To achieve high-fidelity event identification, we perform supervised training on a dataset of simulated 137Cs emissions characterized by varying noise profiles and emission rates and complemented with the ground truth timestamps of the detector hits. Training data were normalized to a range of [0, 1] based on the maximum integer value of the 16-bit ADC to ensure numerical stability during the learning phase.
The architectural implementation relies on HLS4ML, a specialized framework developed by CERN, to translate high-level neural network models into hardware-ready IP cores. The model architecture is optimized for extreme resource efficiency, utilizing only 353 trainable parameters to minimize the footprint on Digital Signal Processing (DSP) slices. To meet stringent real-time requirements, a parallel execution strategy was adopted, enabling data transmission across layers within a single clock cycle. An input window size of 32 words was selected to provide sufficient temporal context for signal classification while maintaining a manageable resource profile. In the firmware layer, a sliding buffer aggregates the serial ADC stream into these 32-word frames to feed the CNN’s input layer.
The model generates an output probability for each timestep via a sigmoid activation function, which is subsequently converted into a binary mask through a tunable real-time threshold. This thresholding logic produces a 32-bit binary string where each bit denotes the presence of a detected hit. To further optimize the FPGA resource utilization, rigorous data-type refinement was conducted, settling on a fixed-point representation of 5 integer and 8 fractional bits.
For a single digitizer channel, this configuration occupies 16.79% of Look-Up Tables (LUTs), 8.91% of Flip-Flops, 8.94% of Block RAMs, and 25.81% of DSP resources on the target device. The low resource occupancy allows for at least two single channel designs to be deployed in conjunction with the core digitizer firmware.
Performance verification via Vivado testbench simulations confirmed a perfect correlation between the hardware implementation and the original Python-based predictions. Operating at the native 125 MS/s sampling rate 8 ns clock period), the application achieves timing closure with an initiation interval of 32 cycles. This ensures constant real-time throughput with a deterministic latency of 130 cycles (1040 ns), facilitating precise coincidence measurements across at least two channels.
For final testing we integrated the system into the readout of a scintillating muon detector which is easy to benchmark against a discriminator setup. This kind of testing will also allow us to understand better the real-world parameters in which this type of system can have an edge over traditional triggering mechanisms.