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Michael Wiebusch (GSI Helmholtzzentrum für Schwerionerforschung GmbH)29/09/2026, 13:40Modules - Module, PCB and Component DesignPoster
A discrete front-end circuit for fast scintillation detectors is presented, enabling simultaneous timing and energy measurement using leading-edge discriminators and TDCs. Instead of relying on time-over-threshold, which is sensitive to pulse shape distortions, the circuit samples the pulse amplitude near its peak, stores it, and converts it into a pulse width via controlled discharge. This...
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10. A Flexible FPGA-based Emulator for Front-End Electronics of the CMS High-Granularity CalorimeterHendrik Alexander Krause (KIT - Karlsruhe Institute of Technology (DE))29/09/2026, 13:40Logic - Digital Design, Verification Tools and MethodsPoster
The CMS Phase-2 High-Granularity Calorimeter (HGCAL) employs a high-bandwidth front-end with significant variations in topology and data rates. To support the back-end firmware development, an FPGA-based front-end emulator has been implemented on a Serenity-S1 FPGA board. The emulator framework uses lpGBT link emulation along with output buffer emulation of the key front-end ASICs. Additional...
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Soumyajit Mandal29/09/2026, 13:40Links - Optoelectronics and Electrical Data LinksPoster
We present a fiber-optic link that simultaneously delivers DC power
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and Manchester-coded slow-control data to a multi-junction GaAs
optical power converter (OPC) operating in a cryogenic environment.
Using a single 808 nm multimode fiber, the link supplies up to 160 mW
of regulated electrical power while transmitting data at 10 kb/s,
with the OPC immersed in liquid nitrogen (LN2) at 77... -
Timo Muscheid29/09/2026, 13:40Logic - Digital Design, Verification Tools and MethodsPoster
Cryogenic detector arrays demand scalable, low-noise readout electronics to preserve their superior energy resolution. Frequency-division multiplexing enables large channel counts but leads to high amplifier power and potential signal distortion when using static carrier tones.
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Continuously tracking the resonance frequencies is mitigating this problem, but requires the readout electronics to... -
Daniel Crovo29/09/2026, 13:40Logic - Digital Design, Verification Tools and MethodsPoster
Multiplexed readout of large cryogenic detector arrays is essential for next-generation particle-physics experiments such as direct neutrino-mass measurements and dark-matter searches. In these systems, online triggering is a key component of the readout chain, enabling real-time pulse detection and selective event storage under low latency and resource utilization constraints. We present a...
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Dmitry Eliseev (Rheinisch Westfaelische Tech. Hoch. (DE))29/09/2026, 13:40Links - Optoelectronics and Electrical Data LinksPoster
The lpGBT is a radiation-tolerant ASIC enabling high-speed optical communication for high-energy physics experiments. To address prototyping challenges in the designs, which include the lpGBT, we present an FMC mezzanine board and the lpGBT Stream IP Core. The mezzanine provides access to eLinks, clocks, GPIOs and configuration interfaces of lpGBT, allowing prototyping without a need for a...
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Juan José Silva García (GRAF (Group of Radio Frequency) - University of Barcelona)29/09/2026, 13:40Integration - Integration, Packaging and InterconnectsPoster
This work optimizes the readout of large-area silicon photomultipliers for time-of-arrival measurements, evaluated in terms of jitter. Unlike conventional direct sensor-to-readout connections, it provides an accurate theoretical characterization of both the sensor and the front-end readout circuit, validated through laboratory measurements, and derives a matching condition to enhance...
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Nikitas Loukas (University of Notre Dame (US)), Piyush Kumar (University of Notre Dame (US)), Stephen Goadhouse (University of Virginia (US))29/09/2026, 13:40Logic - Digital Design, Verification Tools and MethodsPoster
This work presents the firmware architecture and implementation of the Barrel Calorimeter Processor (BCP) for the Phase-2 CMS ECAL Barrel as well as the ECAL refurbishment. The presentation focuses on a single Front-End Driver (FED), addressing resource allocation and key implementation challenges. System performance is validated through a slice test with five Very Front-End (VFE) boards and...
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James Storey (CERN)29/09/2026, 13:40Radiation - Radiation-Tolerant Components and SystemsPoster
Timepix3 hybrid pixel detectors installed inside the CERN SPS beam pipe for a Beam Gas Ionisation profile monitor showed intermittent communication loss, resets and pixel-data corruption with intense multi-bunch beams. Initial investigations considered both radiation-induced single-event effects and electromagnetic interference; dedicated tests indicated an EMI origin. EMC laboratory studies...
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Vladimir Sidorenko (Karlsruher Institut für Technologie)29/09/2026, 13:40Timing & Trigger DistributionPoster
Accurate clock and time distribution is a key requirement for the free-streaming data acquisition of the CBM experiment, where timestamped data are reconstructed online at interaction rates of up to 10 MHz. The Timing and Fast Control system distributes the global clock and time to about 200 readout FPGA boards over a hierarchical network of latency-deterministic optical links. A previous...
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Jasmin Barbara Lebert (Goethe University Frankfurt (DE))29/09/2026, 13:40Logic - Digital Design, Verification Tools and MethodsPoster
The ALICE 3 detector will operate at collision rates of 24 MHz (pp) and 300 kHz (Pb–Pb). The resulting hit occupancies demand higher frequencies in the on-chip digital readout of the pixel sensors. To minimize power consumption, the lowest frequency sustaining loss-free data transmission must be determined.
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This work presents a SystemC simulation of the readout architecture to be integrated... -
Mehmet Alp Sarkisla (Bogazici University (TR))29/09/2026, 13:40Modules - Module, PCB and Component DesignPoster
This work presents a versatile and robust platform board based on the Zynq SoC architecture. The platform is highly adaptable for a broad range of applications, offering features such as differential clock inputs and outputs with jitter-cleaning functionality, QWIIC expansion, and expandable general-purpose QSH and RJ45 connections. The design and implementation are described in detail,...
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Audrey Katherine Kvam (University of Massachusetts (US))29/09/2026, 13:40Timing & Trigger DistributionPoster
The ATLAS High-Luminosity TDAQ upgrade seeks to increase the trigger rate from 100 kHz to 1 MHz and provides additional latency for processing. New electronics for the Monitored Drift Tube chambers (MDTs) make it possible to include this precision muon data in the first level trigger. We designed and implemented an ATCA blade including a Service Module based on the APOLLO platform, together...
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Dr Marc Schneider (KIT - Karlsruhe Institute of Technology)29/09/2026, 13:40Links - Optoelectronics and Electrical Data LinksPoster
Silicon photonic ring modulators are key components for future silicon photonic transmitter systems in particle detectors. It has been shown that standard designs can retain acceptable performance up to a total ionizing dose of approx. 3 MGy, and up to more than 7 MGy when employing annealing techniques. We present a modified design which is expected to increase radiation tolerance...
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Felix Sebastian Nitz (Bergische Universitaet Wuppertal (DE))29/09/2026, 13:40Modules - Module, PCB and Component DesignPoster
The Monitoring of Pixel System (MOPS) chip is an ASIC developed to monitor the ATLAS Inner Tracker Pixel modules. Within the Detector Control System (DCS), the MOPS-Hub aggregates data from multiple MOPS chips. However, further integration through the designated DCS interface remains too complex for deployment at integration sites. To address this, a simplified...
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David Bartunek (University of West Bohemia (CZ))29/09/2026, 13:40Modules - Module, PCB and Component DesignPoster
This work presents the development of a picoTDC-based NIM module for the ARP project at CERN, designed for precision timing in the AFP (ATLAS Forward Proton) Cherenkov detector Roman Pot system. The module integrates a PolarFire FPGA with the picoTDC ASIC developed at CERN, forming a compact and scalable readout unit. It enables high-resolution time-over-threshold measurements and reliable...
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Paolo Musico (INFN e Universita Genova (IT))29/09/2026, 13:40System - System Design, Description and OperationPoster
We report the studies for the design of a cryogenic SiPM based camera.
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It is composed by a SiPM matrix handled by a newly developed ASIC: the DENEB.
This chip measure timing and energy information and transmit data in a fast and configurable way.
The system will be immersed in liquid Argon under a moderate magnetic field: the challenges are to make the system working in this particular... -
Prof. Michele Caselle (INFN Bari and University of Foggia)29/09/2026, 13:40Integration - Integration, Packaging and InterconnectsPoster
2.5D chiplet architectures and 3D wafer‑to‑wafer integration are rapidly becoming indispensable technologies for next‑generation detector development, but access to these advanced processes is still limited and costly for small‑volume R&D. DRD7.6b addresses this barrier by developing in‑house TSV, RDL, interposer, and 3D ASIC‑integration capabilities while reinforcing collaboration with...
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Benoit Rio (European XFEL)29/09/2026, 13:40System - System Design, Description and OperationPoster
The PIXIE (Plasma Interface for XFEL Atmospheric-Pressure Experiments) R&D project at European XFEL investigates a confined high-current thermal arc as an alternative to conventional solid vacuum-to-air interfaces. The plasma behaves as a nonlinear dynamic load, requiring a short DC pulse up to 1.5 kV for breakdown, transiting to a stable 86 V, 20 A arc and allowing continuous power increase...
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Dr Richard Bates (University of Glasgow (GB))29/09/2026, 13:40Integration - Integration, Packaging and InterconnectsPoster
Across a range of materials, SnAg1.8 solder on Cu pillars and indium are widely used in flip-chip bonding for the hybridization of sensor chips to read-out electronics.
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Flip-chip bonding is performed with a range of process to accommodate device specifications and features, for example uneven or curved chips.
Testing a variety of bond parameters such as bond force and developing strategies... -
Zulal Kiraz (CNRS - IJCLab)29/09/2026, 13:401System - System Design, Description and OperationPoster
We present the front-end readout electronics for the LHCb ECAL Phase-II
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upgrade during LS4. The current ECAL will be replaced by PicoCal, designed to sustain higher pile-up, occupancy, and radiation levels with a five-fold increase in granularity across regions with different technologies. PicoCal targets a timing resolution below \SI{15}{ps} over \SI{50}{MeV} to \SI{5}{GeV}, with channel... -
Dominic Ecker (CERN)29/09/2026, 13:40Logic - Digital Design, Verification Tools and MethodsPoster
The ATLAS Detector Control System (DCS) ensures the safe and reliable operation of the detector by providing a standardized interface to all subsystems and infrastructure. The hardware status is currently assessed against static, vendor-defined thresholds and operational status, enforced in the SCADA back-end. The current system is therefore blind to gradual degradation and correlated hardware...
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Andrej Seljak (Jozef Stefan Institute (SI))29/09/2026, 13:40Radiation - Radiation-Tolerant Components and SystemsPoster
Silicon photomultipliers (SiPMs) are candidate photodetectors for the LHCb RICH upgrade II, where they are required to operate reliably in high radiation environments. Critical parameters such as dark count rate, gain stability, and photon detection efficiency were therefore evaluated as a function of neutron fluence. The results indicate a significant increase of DCR, noise and leakage...
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Nikitas Loukas (University of Notre Dame (US))29/09/2026, 13:40Timing & Trigger DistributionPoster
After the Phase-II upgrade of the CERN Large Hadron Collider, precise pile-up discrimination in the CMS Electromagnetic Barrel Calorimeter requires a highly accurate and repeatable clock distribution system. Achieving picosecond-level phase stability across resets is critical to avoid repeated calibration, but standard Field-Programmable Gate Arrays (FPGAs) lack this capability. The Barrel...
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Federico Morodei (Sapienza Universita e INFN, Roma I (IT))29/09/2026, 13:40Timing & Trigger DistributionPoster
The Data Collector and Transmitter (DCT) is a radiation-tolerant FPGA-based board developed for the readout of ATLAS RPC detectors in view of the High-Luminosity LHC upgrade. This contribution presents the hardware test results obtained with the BI-DCT, the DCT version designed for the new BI RPC chambers. Tests performed at CERN with cosmic-ray muons demonstrate excellent timing and spatial...
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Mr Ferran Ortiz (CERN)29/09/2026, 13:401System - System Design, Description and OperationPoster
The ATLAS experiment at the Large Hadron Collider (LHC) will undergo a major upgrade for the High-Luminosity LHC (HL-LHC), enabling operation at luminosities up to 5–7 times the nominal design value. To meet these new challenging conditions, the ATLAS Tile Calorimeter will completely replace its readout electronics with a new architecture based on a fully digital trigger system.
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This... -
Pawel Kozlowski29/09/2026, 13:40Links - Optoelectronics and Electrical Data LinksPoster
The development of high‑speed photonic links for next‑generation detector readout requires precise thermal regulation (±0.5 °C) of the micro‑ring modulators in photonic integrated circuits (PIC). Such stability is needed to maintain resonance alignment and ensure reliable 25 Gbps operation. To evaluate the intended ASIC architecture before fabrication, we built a prototype temperature‑control...
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Konstantinos Alexopoulos (Nat. Cent. for Sci. Res. Demokritos (GR))29/09/2026, 13:40Integration - Integration, Packaging and InterconnectsPoster
The innermost barrel layer of the CMS Phase-2 Inner Tracker will be replaced half way through the HL-LHC lifetime due to the extreme radiation levels. Rather than a simple replacement, an improved Layer-1 design has been developed, targeting a factor of two reduction in mass to improve tracking performance. A new long-ladder high-density interconnect (HDI) was designed for powering and reading...
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Jeongeun Lee (Seoul National University (KR))29/09/2026, 13:40Radiation - Radiation-Tolerant Components and SystemsPoster
Low-Gain Avalanche Diode (LGAD) sensors for the CMS MTD Endcap Timing Layer must retain charge collection (> 8 fC after irradiation) and timing performance at <50 ps level after fluences up to $2.5×10^{15}n_{\mathrm{eq}}/\mathrm{cm}^{2}$, while operating cold ($-25 ^{\circ}\mathrm{C}$) with sufficient bias-voltage margin. We present radiation-tolerance studies of LGAD sensors proton-irradiated...
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Mr Matteo Brini (CAEN S.p.A.)29/09/2026, 13:40Logic - Digital Design, Verification Tools and MethodsPoster
This study proposes a 1D Convolutional Neural Network (CNN) architecture designed for real-time particle hit detection, moving beyond traditional rigid triggering thresholds. By processing continuous data streams, including high-noise environments, our model demonstrates superior sensitivity in low Signal-to-Noise Ratio (SNR) regimes and pile up events. We demonstrate that this approach...
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Tim Stellhorn (Universität Münster (DE))29/09/2026, 13:40Logic - Digital Design, Verification Tools and MethodsPoster
The Sensor Pixel Asynchronous Readout CMOS (SPARC) aims to evaluate the feasibility of implementing an asynchronous readout logic in a monolithic pixel matrix. The design of pixel detectors like SPARC is supported by the PixESL framework, which provides the opportunity to implement a digital prototype at a high level of abstraction. This contribution will focus on PixESL simulations of the...
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WEI Wei weiw ((Institute of High Energy Physics(IHEP))29/09/2026, 13:40Logic - Digital Design, Verification Tools and MethodsPoster
SHINE is a hard X-ray free electron laser device with pulse repetition rates up to 1 MHz, requiring high-speed pixel detectors such as STARLIGHT with target frame rates higher than 10 kHz . In order to meet its high data transmission requirements while enabling portable detector testing, this work developed a firmware architecture based on TB5. This design integrates power transmission,...
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Sabrina Perrella (Sapienza Universita e INFN, Roma I (IT))29/09/2026, 13:40Logic - Digital Design, Verification Tools and MethodsPoster
The upgrade of the muon trigger system of the ATLAS experiment for the HL-LHC introduces new DCT and SL boards to handle increased luminosity and rates. The DCT firmware implements a sub-nanosecond TDC based on oversampling using ISERDES primitives in AMD Xilinx FPGAs. A dedicated test bench was developed to evaluate performance in terms of time resolution, linearity, and behaviour at high...
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Hannes Sakulin (CERN)29/09/2026, 13:40Timing & Trigger DistributionPoster
We present an update on the CMS Phase-2 Global Trigger (GT), the final stage of the new Level-1 trigger that will apply the trigger menu to objects identified by upstream trigger systems. To provide space for up to 1000 cut-based or machine-learning based algorithms, the GT is distributed over thirteen processing boards, each featuring an AMD VU13P FPGA. We report on porting the system to the...
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Nikolaos Trikoupis (CERN)29/09/2026, 13:40System - System Design, Description and OperationPoster
At CERN, the High-Luminosity upgrade of the Large Hadron Collider requires the deployment of approximately 2,000 electronic cards to support 1,800 new cryogenic instrumentation channels, interfacing with an existing base of about 10,000 transducer cards.
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This paper presents the redesign of the instrumentation electronics with respect to the original LHC generation, addressing component... -
Lea Katharina Burmeister (Heidelberg University (DE))29/09/2026, 13:40Timing & Trigger DistributionPoster
While heavy WIMP searches have reached unprecedented sensitivities, light dark matter (LDM) remains largely unexplored. The DELight experiment will probe this regime using superfluid 4He as the target, monitored with MMC-based large-area microcalorimeters (LAMCALs) at mK temperatures, providing excellent energy resolution and eV-scale thresholds.
DELight aims at a deadtime-free DAQ system...
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Jiaguo Zhang (Paul Scherrer Institut)29/09/2026, 13:40System - System Design, Description and OperationPoster
Gotthard-II is a charge-integrating silicon microstrip detector designed for energy-dispersive experiments and X-ray photon beam diagnostics at free-electron lasers (FELs) and synchrotrons. Its scientific applications encompass X-ray absorption and emission spectroscopy, X-ray energy diagnostics, photon arrival-time monitoring, and veto-signal generation for pixel detectors. The Gotthard-II...
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Mr Weiming Qian29/09/2026, 13:40Modules - Module, PCB and Component DesignPoster
To achieve instantaneous luminosities 5-7.5 times of the nominal value of the LHC, it poses significant challenges to the Trigger and Data Acquisition systems during HL-LHC upgrade. A baseline architecture was chosen for the ATLAS Phase-II upgrade, relying on a single-level hardware trigger.The Global Trigger performs complex algorithms
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on full-granularity calorimeter data. The Global Trigger... -
Nils Heyer (Uppsala University)29/09/2026, 13:40System - System Design, Description and OperationPoster
This contribution presents the Radio Neutrino Observatory in Greenland (RNO-G), designed to measure cosmic neutrinos in the EeV range through an array of radio antennas detecting nano-second-long radio flashes. The RNO-G electronic system is outlined, illustrating how signals are measured from the antennas to the recorded pulses. New instrumentation developments are presented, focusing on...
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Felix Frombach29/09/2026, 13:40Logic - Digital Design, Verification Tools and MethodsPoster
The CBM experiment at FAIR will operate a trigger-less free-streaming DAQ at up to 10 MHz collision rate, generating ~1 TB/s of raw data.
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The Timing and Fast-Control (TFC) system provides deterministic timing and will be extended to aggregate readout congestion signals to generate throttle decisions, preventing overflow-induced data loss.
We present a modular UVM simulation of the Silicon... -
Chihiro Yamada (The University of Osaka)29/09/2026, 13:40Timing & Trigger DistributionPoster
The COMET Phase-I experiment at J-PARC searches for muon-to-electron conversion, a charged-lepton-flavour-violating process. The trigger is generated by a multi-stage FPGA-based system using Cylindrical Drift Chamber (CDC) tracking information and timing information from the Cylindrical Trigger Hodoscope (CTH). The CDC tracking trigger system consists of readout boards, trigger front-end and...
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