Speaker
Description
At CERN, the High-Luminosity upgrade of the Large Hadron Collider requires the deployment of approximately 2,000 electronic cards to support 1,800 new cryogenic instrumentation channels, interfacing with an existing base of about 10,000 transducer cards.
This paper presents the redesign of the instrumentation electronics with respect to the original LHC generation, addressing component obsolescence, radiation tolerance, and observed failure modes. The new designs further introduce extended functionality and allow for long-term stability and maintainability. Key architectural choices and design features of the developed card families are discussed.
Summary (500 words)
For the High-Luminosity upgrade of the Large Hadron Collider (HL-LHC), the cryogenic instrumentation team at CERN has designed a new generation of radiation-tolerant electronics. Approximately 2,000 electronic cards will be produced to instrument 1,800 new channels, while ensuring compatibility with the existing infrastructure of around 10,000 transducer cards.
The redesign builds on 18 years of operational experience from the LHC, during which key failure modes were identified and addressed to reduce fault occurrence in future operation. In parallel, component obsolescence has been a major driver: outdated parts have been replaced, and multi-footprint strategies have been introduced to mitigate supply risks and ensure long-term maintainability.
A major design update common to all card families concerns the upgrade of field-programmable gate arrays (FPGAs), replacing legacy anti-fuse technologies with IGLOO®2 FPGA devices. Beyond improved capacity and design flexibility, these FPGAs enable new functionalities such as asset identification storage in embedded non-volatile memory (eNVM), accessed via the High-Performance Memory Subsystem (HPMS).
Radiation qualification has been central to the development. Extensive irradiation campaigns performed in 2016–2018 and 2023–2024 at component and system level validated the selected technologies and design approaches for HL-LHC conditions. For the FPGAs, we achieved zero single-event latch-up (SEL) and no application-level upsets through the application of dedicated design techniques and configuration strategies.
Several card families have been redesigned or newly developed. Around 1,000 Temperature Transducer (TT) cards will be deployed, including high-voltage isolated variants (HV-TT). These integrate updated isolators and improved protection against high-voltage transients in 4-wire measurement channels, addressing issues observed during LHC operation.
The Electrical Heater (EH) card extends previous functionality (linear DC regulation up to 60 VDC and 230 AC switching) with two additional modes: high-voltage DC switching above 100 VDC and a communication-based mode enabling control of external power supplies for load regulation, both providing galvanic isolation for ground-fault operation.
The Level Transducer (LT) card redesign addresses a critical failure mode in the legacy system that could damage cards and crate modules during hot-plugging due to incorrect voltage sequencing. The new design mitigates this issue through updated components and controlled power sequencing.
A new communication card implementing CERN’s NanoFIP standard replaces obsolete WorldFIP modules, ensuring backward compatibility while improving noise immunity via voltage translation between legacy 5 V systems and modern low-voltage electronics.
Finally, a Digital Input/Output (DIDO) card has been developed for cryogenic valve control and status monitoring. It supports both solenoid and piezoelectric actuators, the latter requiring a controlled negative voltage pulse to ensure full closure and prevent leakage due to membrane creep.
All these design updates aim to ensure that the new cards provide reliable operation of the cryogenic instrumentation system following the HL-LHC upgrade of the Large Hadron Collider, while maintaining long-term stability and maintainability. By addressing obsolescence, radiation tolerance, and known failure mechanisms, while introducing enhanced functionality and upgrade capability, the new designs are intended to secure robust and sustained performance under HL-LHC operating conditions.