28 September 2026 to 2 October 2026
Castelldefels, Barcelona, Spain
Europe/Zurich timezone

Prototyping a Temperature Control Unit for Resonant Wavelength Stabilization of a Silicon Photonic Ring Modulator

29 Sept 2026, 13:40
1h 40m
Garraf 1st floor & Aula

Garraf 1st floor & Aula

Poster Links - Optoelectronics and Electrical Data Links Poster 1

Speaker

Pawel Kozlowski

Description

The development of high‑speed photonic links for next‑generation detector readout requires precise thermal regulation (±0.5 °C) of the micro‑ring modulators in photonic integrated circuits (PIC). Such stability is needed to maintain resonance alignment and ensure reliable 25 Gbps operation. To evaluate the intended ASIC architecture before fabrication, we built a prototype temperature‑control unit using a mixed-signal platform combining an FPGA with discrete analog components. A custom PCB featuring an ADC and a DAC was designed and characterized. The FPGA hosted the control logic. The prototype was connected to a CERN-developed PIC, and closed‑loop stabilization with 40kHz sampling frequency was demonstrated.

Summary (500 words)

Future particle detector readout systems rely on co integration of PICs and ASICs to achieve stable, high bandwidth optical communication (25 Gbps per channel). Although the prototype targets a single micro-ring modulator (MRM), the final design will employ wavelength-division multiplexing with four wavelengths to reach an aggregate data rate of 100 Gbps per link. Because the resonance wavelength of an MRM is highly sensitive to temperature changes, fast and accurate thermal control (±0.5 °C on millisecond timescales) is required to initialize and maintain wavelength locking to ensure robust operation. To support ASIC development ahead of tape out, a prototype Temperature Control Unit (TCU) was conceived, assembled, and evaluated. Its purpose was to validate the control architecture, provide early insight into achievable performance, and offer a realistic hardware platform for algorithm development.

The prototype system mirrors the intended ASIC architecture by combining FPGA-based digital logic with discrete analog circuitry. A dedicated PCB hosting an ADC and a DAC was fabricated, while the FPGA implements the temperature control algorithms and communication interfaces. The test system was completed by connecting the TCU to the CERN-developed PIC.

Comprehensive characterization was performed at both component and system levels, including ADC/DAC performance measurements, TCU initialization procedures, and closed loop stabilization of the MRM. The system’s robustness was assessed under varying disturbance conditions (up to ±3 °C aggressor pulses with rise/fall times from microseconds to milliseconds) and across different control loop parameters. Optical eye diagram monitoring was used to correlate thermal control performance with optical-signal quality, and automated long term stress tests were conducted to evaluate reliability and repeatability.

The prototype successfully achieved stable closed-loop temperature regulation of the MRM and validated the entire sensing-to-actuation chain. Although the discrete ADC and DAC offer lower Effective Number of Bits and worse linearity than the final ASIC versions, the system operated reliably and provided valuable pre-fabrication feedback to the ASIC design team. This work establishes a robust experimental platform that supports ongoing development of photonic readout links for high-energy physics applications.

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