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Description
The upgrade of the muon trigger system of the ATLAS experiment for the HL-LHC introduces new DCT and SL boards to handle increased luminosity and rates. The DCT firmware implements a sub-nanosecond TDC based on oversampling using ISERDES primitives in AMD Xilinx FPGAs. A dedicated test bench was developed to evaluate performance in terms of time resolution, linearity, and behaviour at high rates. Results demonstrate sub-nanosecond precision and reliable operation under realistic conditions, validating the system for deployment in the ATLAS upgrade.
Summary (500 words)
The Muon System of the ATLAS Experiment at the CERN Large Hadron Collider (LHC) will be upgraded to deal with the increased luminosity and rates expected during High-Luminosity operation (HL-LHC). The Level-0 Muon Barrel Trigger System electronics will be replaced by new on-detector Data Collector and Transmitter (DCT) boards and new off-detector Sector Logic (SL) boards. The DCT has been developed to read out up to 288 RPC channels, and to measure and digitize the arrival time of detector signals with respect to the 40 MHz LHC clock. Once zero-suppressed, the data is transmitted via optical links to the Barrel SLs where the implemented trigger processor runs a coincidence algorithm using the data coming from the four layers of RPC detectors via the DCTs.
To meet the requirements for precise time measurement of detector hits, the DCT firmware implements a sub-nanosecond Time-to-Digital Converter (TDC) based on the oversampling technique. It uses the high-speed ISERDES primitives available in the AMD Xilinx FPGAs, running at 600 Mb/s in DDR mode. This approach achieves fine time quantization with limited FPGA resource usage, making it compatible with relatively small FPGAs even in applications with a high number of input channels, such as in the DCT.
To characterize the FPGA-TDC, a dedicated test bench was developed, consisting of custom boards capable of generating programmable, RPC-like pulses. These boards allow precise control of the timing and width of the pulses, the delays among different channels, and the hit multiplicity.
The TDC performance was evaluated by checking its time resolution, linearity, and the agreement between measurements from different channels. In addition, the dependence on pulse width and the double-hit resolution were investigated, together with the behaviour under high rates, to emulate realistic detector occupancy conditions. Attention was given to the impact of clock quality and sampling phase alignment on the timing performance. System-level validation, including zero suppression and data transmission, was also performed.